diff options
| author | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-26 13:36:44 +0300 |
|---|---|---|
| committer | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-26 13:36:44 +0300 |
| commit | 3addbc0ee49e4a7d841150d944b6a0984919cbeb (patch) | |
| tree | efeb682a70d4e9faf1465a3f9e128bdc3d1b6a1e /arch | |
| parent | fd6f56903b35318b2a1b79d14ad092a57d08149a (diff) | |
| download | linux-3addbc0ee49e4a7d841150d944b6a0984919cbeb.tar.xz | |
add timer device and modify timer clk config
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 8eb1261b6682..a35167a3b70b 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -569,6 +569,27 @@ status = "disabled"; }; + timer: timer@12480000 { + compatible = "starfive,timers"; + reg = <0x0 0x12480000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <76>, <77>, <78> ,<79>, <80>, <81>, <82>, <83>; + clocks = <&clkgen JH7100_CLK_TIMER0_CORE>, + <&clkgen JH7100_CLK_TIMER1_CORE>, + <&clkgen JH7100_CLK_TIMER2_CORE>, + <&clkgen JH7100_CLK_TIMER3_CORE>, + <&clkgen JH7100_CLK_WDT_CORE>, + <&clkgen JH7100_CLK_TIMER4_CORE>, + <&clkgen JH7100_CLK_TIMER5_CORE>, + <&clkgen JH7100_CLK_TIMER6_CORE>, + <&clkgen JH7100_CLK_WDTIMER_APB>; + clock-names = "timer0", "timer1", "timer2", + "timer3", "wdog", "timer4", + "timer5", "timer6", "apb_clk"; + clock-frequency = <50000000>; + status = "okay"; + }; + watchdog@12480000 { compatible = "starfive,si5-wdt"; reg = <0x0 0x12480000 0x0 0x10000>; |