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| author | H. Peter Anvin <hpa@linux.intel.com> | 2014-05-22 02:23:19 +0400 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-05-22 02:23:19 +0400 |
| commit | e6ab9a20e73e790d47e6aa231fcf66f27b6ce3d4 (patch) | |
| tree | 6a41361e1de2a6693ccae96b99307e79a467236f /arch/xtensa/mm/cache.c | |
| parent | 34273f41d57ee8d854dcd2a1d754cbb546cb548f (diff) | |
| parent | 7ed6fb9b5a5510e4ef78ab27419184741169978a (diff) | |
| download | linux-e6ab9a20e73e790d47e6aa231fcf66f27b6ce3d4.tar.xz | |
Merge commit '7ed6fb9b5a5510e4ef78ab27419184741169978a' into x86/espfix
Merge in Linus' tree with:
fa81511bb0bb x86-64, modify_ldt: Make support for 16-bit segments a runtime option
... reverted, to avoid a conflict. This commit is no longer necessary
with the proper fix in place.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/xtensa/mm/cache.c')
| -rw-r--r-- | arch/xtensa/mm/cache.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index ba4c47f291b1..63cbb867dadd 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -59,6 +59,10 @@ * */ +#if (DCACHE_WAY_SIZE > PAGE_SIZE) && defined(CONFIG_HIGHMEM) +#error "HIGHMEM is not supported on cores with aliasing cache." +#endif + #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK /* @@ -179,10 +183,11 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep) #else if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) && (vma->vm_flags & VM_EXEC) != 0) { - unsigned long paddr = (unsigned long) page_address(page); + unsigned long paddr = (unsigned long)kmap_atomic(page); __flush_dcache_page(paddr); __invalidate_icache_page(paddr); set_bit(PG_arch_1, &page->flags); + kunmap_atomic((void *)paddr); } #endif } |