diff options
| author | James Morse <james.morse@arm.com> | 2021-07-28 20:06:31 +0300 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-08-11 18:58:33 +0300 |
| commit | 141739aa73505539f315d15068b9c0707ab5ecb4 (patch) | |
| tree | 27f47a8028065f00b7fb167e9685e6995e21eb99 /arch/x86/kernel | |
| parent | fa8f711d2f14381d1a47420b6da94b62e6484c56 (diff) | |
| download | linux-141739aa73505539f315d15068b9c0707ab5ecb4.tar.xz | |
x86/resctrl: Make ctrlval arrays the same size
The CODE and DATA resources report a num_closid that is half the actual
size supported by the hardware. This behaviour is visible to user-space
when CDP is enabled.
The CODE and DATA resources have their own ctrlval arrays which are
half the size of the underlying hardware because num_closid was already
adjusted. One holds the odd configurations values, the other even.
Before the CDP resources can be merged, the 'half the closids' behaviour
needs to be implemented by schemata_list_create(), but this causes the
ctrl_val[] array to be full sized.
Remove the logic from the architecture specific rdt_get_cdp_config()
setup, and add it to schemata_list_create(). Functions that walk all the
configurations, such as domain_setup_ctrlval() and reset_all_ctrls(),
take num_closid directly from struct rdt_hw_resource also have
to halve num_closid as only the lower half of each array is in
use. domain_setup_ctrlval() and reset_all_ctrls() both copy struct
rdt_hw_resource's num_closid to a struct msr_param. Correct the value
here.
This is temporary as a subsequent patch will merge all three ctrl_val[]
arrays such that when CDP is in use, the CODA/DATA layout in the array
matches the hardware. reset_all_ctrls()'s loop over the whole of
ctrl_val[] is not touched as this is harmless, and will be required as
it is once the resources are merged.
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Link: https://lkml.kernel.org/r/20210728170637.25610-19-james.morse@arm.com
Diffstat (limited to 'arch/x86/kernel')
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/core.c | 10 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/rdtgroup.c | 9 |
2 files changed, 18 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 755118a9ef38..9f8be5ee5e8a 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -363,7 +363,7 @@ static void rdt_get_cdp_config(int level, int type) struct rdt_resource *r = &rdt_resources_all[type].r_resctrl; struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); - hw_res->num_closid = hw_res_l->num_closid / 2; + hw_res->num_closid = hw_res_l->num_closid; r->cache.cbm_len = r_l->cache.cbm_len; r->default_ctrl = r_l->default_ctrl; r->cache.shareable_bits = r_l->cache.shareable_bits; @@ -549,6 +549,14 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) m.low = 0; m.high = hw_res->num_closid; + + /* + * temporary: the array is full-size, but cat_wrmsr() still re-maps + * the index. + */ + if (hw_res->conf_type != CDP_NONE) + m.high /= 2; + hw_res->msr_update(d, &m, r); return 0; } diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 61037b239327..299af12c9fe4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2154,6 +2154,8 @@ static int schemata_list_create(void) s->res = r; s->conf_type = resctrl_to_arch_res(r)->conf_type; s->num_closid = resctrl_arch_get_num_closid(r); + if (resctrl_arch_get_cdp_enabled(r->rid)) + s->num_closid /= 2; ret = snprintf(s->name, sizeof(s->name), r->name); if (ret >= sizeof(s->name)) { @@ -2377,6 +2379,13 @@ static int reset_all_ctrls(struct rdt_resource *r) msr_param.high = hw_res->num_closid; /* + * temporary: the array is full-sized, but cat_wrmsr() still re-maps + * the index. + */ + if (hw_res->cdp_enabled) + msr_param.high /= 2; + + /* * Disable resource control for this resource by setting all * CBMs in all domains to the maximum mask value. Pick one CPU * from each domain to update the MSRs below. |