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| author | Peter Zijlstra <peterz@infradead.org> | 2017-12-22 12:20:12 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-01-14 22:18:23 +0300 |
| commit | 6d671e1b85c63e7a337ba76c1a154c091545cff8 (patch) | |
| tree | 7093ebb0bdc7c2162b5cbbf1c04119056090a427 /arch/x86/kernel/tsc.c | |
| parent | 30c7e5b123673d5e570e238dbada2fb68a87212c (diff) | |
| download | linux-6d671e1b85c63e7a337ba76c1a154c091545cff8.tar.xz | |
x86/time: Unconditionally register legacy timer interrupt
Even without a PIC/PIT the legacy timer interrupt is required for HPET in
legacy replacement mode.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: len.brown@intel.com
Cc: rui.zhang@intel.com
Link: https://lkml.kernel.org/r/20171222092243.382623763@infradead.org
Diffstat (limited to 'arch/x86/kernel/tsc.c')
0 files changed, 0 insertions, 0 deletions