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| author | Krish Sadhukhan <krish.sadhukhan@oracle.com> | 2020-09-18 00:20:36 +0300 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-09-18 11:46:41 +0300 |
| commit | 5866e9205b47a983a77ebc8654949f696342f2ab (patch) | |
| tree | abdb11c74714c51902b260990139d5536cf0df02 /arch/x86/kernel/cpu/scattered.c | |
| parent | 33b4711df4c1b3aec7c267c60fc24abccfadd40c (diff) | |
| download | linux-5866e9205b47a983a77ebc8654949f696342f2ab.tar.xz | |
x86/cpu: Add hardware-enforced cache coherency as a CPUID feature
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a system,
it is not required for software to flush the page from all CPU caches in the
system prior to changing the value of the C-bit for a page. This hardware-
enforced cache coherency is indicated by EAX[10] in CPUID leaf 0x8000001f.
[ bp: Use one of the free slots in word 3. ]
Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200917212038.5090-2-krish.sadhukhan@oracle.com
Diffstat (limited to 'arch/x86/kernel/cpu/scattered.c')
| -rw-r--r-- | arch/x86/kernel/cpu/scattered.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 62b137c3c97a..3221b71a0df8 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 }, + { X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 }, { 0, 0, 0, 0, 0 } }; |