diff options
| author | Hans Rosenfeld <hans.rosenfeld@amd.com> | 2010-10-29 19:14:32 +0400 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2010-11-18 17:53:06 +0300 |
| commit | f658bcfb2607bf0808966a69cf74135ce98e5c2d (patch) | |
| tree | a01f768fb6b49acd701f912f426e1fd6ee4f0f56 /arch/x86/kernel/amd_nb.c | |
| parent | 9653a5c76c8677b05b45b3b999d3b39988d2a064 (diff) | |
| download | linux-f658bcfb2607bf0808966a69cf74135ce98e5c2d.tar.xz | |
x86, cacheinfo: Cleanup L3 cache index disable support
Adaptions to the changes of the AMD northbridge caching code: instead
of a bool in each l3 struct, use a flag in amd_northbridges.flags to
indicate L3 cache index disable support; use a pointer to the whole
northbridge instead of the misc device in the l3 struct; simplify the
initialisation; dynamically generate sysfs attribute array.
Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'arch/x86/kernel/amd_nb.c')
| -rw-r--r-- | arch/x86/kernel/amd_nb.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 63c8b4f2c1ad..affacb5e0065 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -68,6 +68,16 @@ int amd_cache_northbridges(void) boot_cpu_data.x86 == 0x15) amd_northbridges.flags |= AMD_NB_GART; + /* + * Some CPU families support L3 Cache Index Disable. There are some + * limitations because of E382 and E388 on family 0x10. + */ + if (boot_cpu_data.x86 == 0x10 && + boot_cpu_data.x86_model >= 0x8 && + (boot_cpu_data.x86_model > 0x9 || + boot_cpu_data.x86_mask >= 0x1)) + amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); |