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| author | Uros Bizjak <ubizjak@gmail.com> | 2020-05-08 12:22:47 +0300 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-05-12 17:05:30 +0300 |
| commit | 7e32a9dac9926241d56851e1517c9391d39fb48e (patch) | |
| tree | 688bba360ea401a90685c7bcb0d786540577576c /arch/x86/include/asm/invpcid.h | |
| parent | e2abfc0448a46d8a137505aa180caf14070ec535 (diff) | |
| download | linux-7e32a9dac9926241d56851e1517c9391d39fb48e.tar.xz | |
x86/cpu: Use INVPCID mnemonic in invpcid.h
The current minimum required version of binutils is 2.23, which supports
the INVPCID instruction mnemonic. Replace the byte-wise specification of
INVPCID with the proper mnemonic.
[ bp: Add symbolic operand names for increased readability and flip
their order like the insn expects them for the AT&T syntax. ]
Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200508092247.132147-1-ubizjak@gmail.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/include/asm/invpcid.h')
| -rw-r--r-- | arch/x86/include/asm/invpcid.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/x86/include/asm/invpcid.h b/arch/x86/include/asm/invpcid.h index 989cfa86de85..734482afbf81 100644 --- a/arch/x86/include/asm/invpcid.h +++ b/arch/x86/include/asm/invpcid.h @@ -12,12 +12,9 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr, * stale TLB entries and, especially if we're flushing global * mappings, we don't want the compiler to reorder any subsequent * memory accesses before the TLB flush. - * - * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and - * invpcid (%rcx), %rax in long mode. */ - asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : : "m" (desc), "a" (type), "c" (&desc) : "memory"); + asm volatile("invpcid %[desc], %[type]" + :: [desc] "m" (desc), [type] "r" (type) : "memory"); } #define INVPCID_TYPE_INDIV_ADDR 0 |