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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-08-26 18:32:42 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-08-31 14:59:37 +0300 |
| commit | f01d7d558e1855d4aa8e927b86111846536dd476 (patch) | |
| tree | 0303cf3debad568d691a16cc83f1372f7952517c /arch/x86/events | |
| parent | 67c5d44384f8dc57e1c1b3040423cfce99b578cd (diff) | |
| download | linux-f01d7d558e1855d4aa8e927b86111846536dd476.tar.xz | |
perf/x86/intel/uncore: Fix Intel SPR M2PCIE event constraints
Similar to the ICX M2PCIE events, some of the SPR M2PCIE events also
have constraints. Add the constraints for SPR M2PCIE.
Fixes: f85ef898f884 ("perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-7-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 2d75d212c8cc..cd53057fd52d 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5690,9 +5690,16 @@ static struct intel_uncore_type spr_uncore_irp = { }; +static struct event_constraint spr_uncore_m2pcie_constraints[] = { + UNCORE_EVENT_CONSTRAINT(0x14, 0x3), + UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), + EVENT_CONSTRAINT_END +}; + static struct intel_uncore_type spr_uncore_m2pcie = { SPR_UNCORE_COMMON_FORMAT(), .name = "m2pcie", + .constraints = spr_uncore_m2pcie_constraints, }; static struct intel_uncore_type spr_uncore_pcu = { |