diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2020-10-19 18:35:25 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-10-29 13:00:39 +0300 |
| commit | b14d0db5b8c86507c9810c1c8162c7d4a3c656bd (patch) | |
| tree | c04ab1e77bf7ea65f40bab1fa8f3936a4f8e5e52 /arch/x86/events | |
| parent | 51b646b2d9f84d6ff6300e3c1d09f2be4329a424 (diff) | |
| download | linux-b14d0db5b8c86507c9810c1c8162c7d4a3c656bd.tar.xz | |
perf/x86/intel: Add Rocket Lake CPU support
From the perspective of Intel PMU, Rocket Lake is the same as Ice Lake
and Tiger Lake. Share the perf code with them.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201019153528.13850-1-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/intel/core.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 71860986dcb7..4d70c7d6c750 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5436,6 +5436,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_ICELAKE: case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: + case INTEL_FAM6_ROCKETLAKE: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); |