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authorChris Metcalf <cmetcalf@tilera.com>2012-07-18 20:06:19 +0400
committerChris Metcalf <cmetcalf@tilera.com>2012-07-19 00:54:16 +0400
commitf6d2ce00da145ae31ec22d21daca6ca5e22b3c84 (patch)
treebb030290bc253b37bfad91de618c6f080f0b0af9 /arch/tile/include
parentf1006257893917dfb1e0d74cb47b18c0e2908693 (diff)
downloadlinux-f6d2ce00da145ae31ec22d21daca6ca5e22b3c84.tar.xz
tile: updates to pci root complex from community feedback
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include')
-rw-r--r--arch/tile/include/asm/pci.h27
1 files changed, 8 insertions, 19 deletions
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 553b7ff018c4..302cdf71ceed 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -128,15 +128,10 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())
/*
- * End of the PCI memory resource.
+ * Start of the PCI memory resource, which starts at the end of the
+ * maximum system physical RAM address.
*/
-#define TILE_PCI_MEM_END \
- ((1ULL << CHIP_PA_WIDTH()) + TILE_PCI_BAR_WINDOW_TOP)
-
-/*
- * Start of the PCI memory resource.
- */
-#define TILE_PCI_MEM_START (TILE_PCI_MEM_END - TILE_PCI_BAR_WINDOW_SIZE)
+#define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH())
/*
* Structure of a PCI controller (host bridge) on Gx.
@@ -159,17 +154,19 @@ struct pci_controller {
int index; /* PCI domain number */
struct pci_bus *root_bus;
+ /* PCI memory space resource for this controller. */
+ struct resource mem_space;
+ char mem_space_name[32];
+
uint64_t mem_offset; /* cpu->bus memory mapping offset. */
- int last_busno;
+ int first_busno;
struct pci_ops *ops;
/* Table that maps the INTx numbers to Linux irq numbers. */
int irq_intx_table[4];
- struct resource mem_space;
-
/* Address ranges that are routed to this controller/bridge. */
struct resource mem_resources[3];
};
@@ -179,14 +176,6 @@ extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
- struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
- struct pci_bus_region *region);
-
/*
* The PCI address space does not equal the physical memory address
* space (we have an IOMMU). The IDE and SCSI device layers use this