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| author | Jisheng Zhang <jszhang@kernel.org> | 2023-09-12 10:22:32 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-10-17 22:00:24 +0300 |
| commit | 759426c758c7053a941a4c06c7571461439fcff6 (patch) | |
| tree | f67394584e648e740de41620bc3b5373152e8cd7 /arch/riscv | |
| parent | e4078ebbddf69f5a82f164dc07d50321b7f641cf (diff) | |
| download | linux-759426c758c7053a941a4c06c7571461439fcff6.tar.xz | |
riscv: dts: thead: set dma-noncoherent to soc bus
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/thead/th1520.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..ff364709a6df 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -139,6 +139,7 @@ interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; plic: interrupt-controller@ffd8000000 { |