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| author | Greentime Hu <greentime.hu@sifive.com> | 2019-12-19 09:44:59 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-12-20 14:32:24 +0300 |
| commit | d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7 (patch) | |
| tree | d98782836429105d82651dcf854cbb42799a1132 /arch/riscv/mm | |
| parent | 0312a3d4b43c0045869379affc0e228e36411c78 (diff) | |
| download | linux-d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7.tar.xz | |
riscv: fix scratch register clearing in M-mode.
This patch fixes that the sscratch register clearing in M-mode. It cleared
sscratch register in M-mode, but it should clear mscratch register. That will
cause kernel trap if the CPU core doesn't support S-mode when trying to access
sscratch.
Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/mm')
0 files changed, 0 insertions, 0 deletions