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| author | Alex Guo <xfguo@jlsemi.com> | 2018-07-29 04:14:47 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-13 18:31:30 +0300 |
| commit | a89757daf25cfe5320a5f40773271d86e2456c10 (patch) | |
| tree | f9b2fde77d6093253ae8b73be93530486e6c8781 /arch/riscv/lib | |
| parent | 4938c79bd0f5f3650c8c2cd4cdc972f0a6962ce4 (diff) | |
| download | linux-a89757daf25cfe5320a5f40773271d86e2456c10.tar.xz | |
RISC-V: implement __lshrti3.
Signed-off-by: Alex Guo <xfguo@jlsemi.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/lib/tishift.S | 42 |
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 596c2ca40d63..445ec84f9a47 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -2,5 +2,6 @@ lib-y += delay.o lib-y += memcpy.o lib-y += memset.o lib-y += uaccess.o +lib-y += tishift.o lib-$(CONFIG_32BIT) += udivdi3.o diff --git a/arch/riscv/lib/tishift.S b/arch/riscv/lib/tishift.S new file mode 100644 index 000000000000..69abb1277234 --- /dev/null +++ b/arch/riscv/lib/tishift.S @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2018 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + .globl __lshrti3 +__lshrti3: + beqz a2, .L1 + li a5,64 + sub a5,a5,a2 + addi sp,sp,-16 + sext.w a4,a5 + blez a5, .L2 + sext.w a2,a2 + sll a4,a1,a4 + srl a0,a0,a2 + srl a1,a1,a2 + or a0,a0,a4 + sd a1,8(sp) + sd a0,0(sp) + ld a0,0(sp) + ld a1,8(sp) + addi sp,sp,16 + ret +.L1: + ret +.L2: + negw a4,a4 + srl a1,a1,a4 + sd a1,0(sp) + sd zero,8(sp) + ld a0,0(sp) + ld a1,8(sp) + addi sp,sp,16 + ret |