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| author | Anup Patel <anup.patel@wdc.com> | 2020-08-17 15:42:49 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-08-20 20:57:29 +0300 |
| commit | 2ac6795fcc085e8d03649f1bbd0d70aaff612cad (patch) | |
| tree | dfefdd222a88f7c4fae17de7affd5c954a42dd91 /arch/riscv/kernel/smpboot.c | |
| parent | cc7f3f72dc2ae2b383142896d79ca1e237ad7e8b (diff) | |
| download | linux-2ac6795fcc085e8d03649f1bbd0d70aaff612cad.tar.xz | |
clocksource/drivers: Add CLINT timer driver
We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
RISC-V NoMMU kernel).
The CLINT MMIO device provides three things:
1. 64bit free running counter register
2. 64bit per-CPU time compare registers
3. 32bit per-CPU inter-processor interrupt registers
Unlike other timer devices, CLINT provides IPI registers along with
timer registers. To use CLINT IPI registers, the CLINT timer driver
provides IPI related callbacks to arch/riscv.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Emil Renner Berhing <kernel@esmil.dk>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/kernel/smpboot.c')
0 files changed, 0 insertions, 0 deletions