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| author | Palmer Dabbelt <palmer@sifive.com> | 2017-11-29 01:06:17 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-29 01:06:17 +0300 |
| commit | c901e45a999a1935d7adf653e1cf12dfbcd737aa (patch) | |
| tree | 2d30d6656ef0d3fd57f78045830b9c21ae69a5ae /arch/riscv/include | |
| parent | 21db403660d1433b8a02b26d5d4084921b857c40 (diff) | |
| download | linux-c901e45a999a1935d7adf653e1cf12dfbcd737aa.tar.xz | |
RISC-V: `sfence.vma` orderes the instruction cache
This is just a comment change, but it's one that bit me on the mailing
list. It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering. This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.
CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/tlbflush.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 5ee4ae370b5e..c79fab3d377d 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -17,7 +17,10 @@ #ifdef CONFIG_MMU -/* Flush entire local TLB */ +/* + * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction + * cache as well, so a 'fence.i' is not necessary. + */ static inline void local_flush_tlb_all(void) { __asm__ __volatile__ ("sfence.vma" : : : "memory"); |