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authorChanghuang Liang <changhuang.liang@starfivetech.com>2023-06-05 12:48:28 +0300
committerChanghuang Liang <changhuang.liang@starfivetech.com>2023-06-20 09:09:58 +0300
commitd1137517f393b7db5b0377a8ac7d937a24554892 (patch)
tree14ad33731c20a444d6707c0349fdc092ca17ec47 /arch/riscv/boot
parent4964ce0a869e92df26331833894c9d0fd84d80f3 (diff)
downloadlinux-d1137517f393b7db5b0377a8ac7d937a24554892.tar.xz
riscv: dts: starfive: jh7110: Add ov4689 configure
Add ov4689 configure. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Diffstat (limited to 'arch/riscv/boot')
-rwxr-xr-xarch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi
index 05537109bc12..7240d537c8d4 100755
--- a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi
@@ -555,6 +555,24 @@
};
};
+ ov4689: ov4689@36 {
+ compatible = "ovti,ov4689";
+ reg = <0x36>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ //reset-gpio = <&gpio 18 0>;
+ rotation = <180>;
+
+ port {
+ /* Parallel bus endpoint */
+ ov4689_to_csi2rx0: endpoint {
+ remote-endpoint = <&csi2rx0_from_ov4689>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
};
&sdio0 {
@@ -615,6 +633,15 @@
lane-polarities = <0 0 0>;
status = "okay";
};
+
+ csi2rx0_from_ov4689: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&ov4689_to_csi2rx0>;
+ bus-type = <4>; /* MIPI CSI-2 D-PHY */
+ clock-lanes = <4>;
+ data-lanes = <0 1>;
+ status = "okay";
+ };
};
};
};