diff options
| author | Minda Chen <minda.chen@starfivetech.com> | 2024-06-21 11:22:31 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-07-01 15:20:19 +0300 |
| commit | 2904244a8c46bdd0fee181df693a495f4628a575 (patch) | |
| tree | 7bc75b3d3cdbba50787d019466910bf6700da4a7 /arch/riscv/boot/dts/starfive/jh7110-common.dtsi | |
| parent | 3f41368fbfe1b3d5922d317fe1a0a0cab6846802 (diff) | |
| download | linux-2904244a8c46bdd0fee181df693a495f4628a575.tar.xz | |
riscv: dts: starfive: add PCIe dts configuration for JH7110
Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has
one exposed PCIe port, so only the Mars and VisionFive 2 get two
enabled.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
[conor: squash in star64's single exposed port]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot/dts/starfive/jh7110-common.dtsi')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 37b4c294ffcc..20bc8c03b821 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -294,6 +294,20 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; +}; + &pwmdac { pinctrl-names = "default"; pinctrl-0 = <&pwmdac_pins>; @@ -473,6 +487,54 @@ }; }; + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = <GPIOMUX(27, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(32, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = <GPIOMUX(29, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(21, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + pwmdac_pins: pwmdac-0 { pwmdac-pins { pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, |