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| author | Michael Ellerman <michael@ellerman.id.au> | 2007-10-15 13:34:38 +0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2007-10-15 22:29:49 +0400 |
| commit | 2843e7f7d6ffd61da6fe1503eb42c25fa33fbfee (patch) | |
| tree | b4060d6c42fb301c5e718e37ec9a1b0e5319d6fc /arch/powerpc | |
| parent | cdbd3865acc2e98a349b41d130985e6f5f2dfc19 (diff) | |
| download | linux-2843e7f7d6ffd61da6fe1503eb42c25fa33fbfee.tar.xz | |
Remove msic_dcr_read() in axon_msi.c
msic_dcr_read() doesn't really do anything useful, just replace it with
direct calls to dcr_read().
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/platforms/cell/axon_msi.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index aca15007a01c..095988f13bf4 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -80,18 +80,13 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) dcr_write(msic->dcr_host, dcr_n, val); } -static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) -{ - return dcr_read(msic->dcr_host, dcr_n); -} - static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) { struct axon_msic *msic = get_irq_data(irq); u32 write_offset, msi; int idx; - write_offset = msic_dcr_read(msic, MSIC_WRITE_OFFSET_REG); + write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); /* write_offset doesn't wrap properly, so we have to mask it */ @@ -306,7 +301,7 @@ static int axon_msi_notify_reboot(struct notifier_block *nb, list_for_each_entry(msic, &axon_msic_list, list) { pr_debug("axon_msi: disabling %s\n", msic->irq_host->of_node->full_name); - tmp = msic_dcr_read(msic, MSIC_CTRL_REG); + tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; msic_dcr_write(msic, MSIC_CTRL_REG, tmp); } |