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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-03-27 00:47:34 +0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-03-28 04:33:24 +0400 |
| commit | 1ce447b90f3e71c81ae59e0062bc305ef267668b (patch) | |
| tree | 516f26debf251a7aa1538f72710f956b95a2f05c /arch/powerpc/perf/ppc970-pmu.c | |
| parent | cb52d8970eee65bf2c47d9a91bd4f58b17f595f4 (diff) | |
| download | linux-1ce447b90f3e71c81ae59e0062bc305ef267668b.tar.xz | |
powerpc/perf: Fix instruction address sampling on 970 and Power4
970 and Power4 don't support "continuous sampling" which means that
when we aren't in marked instruction sampling mode (marked events),
SIAR isn't updated with the last instruction sampled before the
perf interrupt. On those processors, we must thus use the exception
SRR0 value as the sampled instruction pointer.
Those processors also don't support the SIPR and SIHV bits in MMCRA
which means we need some kind of heuristic to decide if SIAR values
represent kernel or user addresses.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/perf/ppc970-pmu.c')
| -rw-r--r-- | arch/powerpc/perf/ppc970-pmu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/perf/ppc970-pmu.c b/arch/powerpc/perf/ppc970-pmu.c index 111eb25bb0b6..20139ceeacf6 100644 --- a/arch/powerpc/perf/ppc970-pmu.c +++ b/arch/powerpc/perf/ppc970-pmu.c @@ -487,6 +487,7 @@ static struct power_pmu ppc970_pmu = { .n_generic = ARRAY_SIZE(ppc970_generic_events), .generic_events = ppc970_generic_events, .cache_events = &ppc970_cache_events, + .flags = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING, }; static int __init init_ppc970_pmu(void) |