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| author | Arjan van de Ven <arjan@linux.intel.com> | 2008-10-17 20:20:26 +0400 |
|---|---|---|
| committer | Arjan van de Ven <arjan@linux.intel.com> | 2008-10-17 20:20:26 +0400 |
| commit | 651dab4264e4ba0e563f5ff56f748127246e9065 (patch) | |
| tree | 016630974bdcb00fe529b673f96d389e0fd6dc94 /arch/powerpc/oprofile | |
| parent | 40b8606253552109815786e5d4b0de98782d31f5 (diff) | |
| parent | 2e532d68a2b3e2aa6b19731501222069735c741c (diff) | |
| download | linux-651dab4264e4ba0e563f5ff56f748127246e9065.tar.xz | |
Merge commit 'linus/master' into merge-linus
Conflicts:
arch/x86/kvm/i8254.c
Diffstat (limited to 'arch/powerpc/oprofile')
| -rw-r--r-- | arch/powerpc/oprofile/cell/vma_map.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/oprofile/op_model_power4.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/oprofile/cell/vma_map.c b/arch/powerpc/oprofile/cell/vma_map.c index fff66662d021..258fa4411e9e 100644 --- a/arch/powerpc/oprofile/cell/vma_map.c +++ b/arch/powerpc/oprofile/cell/vma_map.c @@ -229,7 +229,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu, */ overlay_tbl_offset = vma_map_lookup(map, ovly_table_sym, aSpu, &grd_val); - if (overlay_tbl_offset < 0) { + if (overlay_tbl_offset > 0x10000000) { printk(KERN_ERR "SPU_PROF: " "%s, line %d: Error finding SPU overlay table\n", __func__, __LINE__); diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c index 446a8bbb847b..3e3d91f536e0 100644 --- a/arch/powerpc/oprofile/op_model_power4.c +++ b/arch/powerpc/oprofile/op_model_power4.c @@ -64,7 +64,7 @@ static int power4_reg_setup(struct op_counter_config *ctr, return 0; } -extern void ppc64_enable_pmcs(void); +extern void ppc_enable_pmcs(void); /* * Older CPUs require the MMCRA sample bit to be always set, but newer @@ -91,7 +91,7 @@ static int power4_cpu_setup(struct op_counter_config *ctr) unsigned int mmcr0 = mmcr0_val; unsigned long mmcra = mmcra_val; - ppc64_enable_pmcs(); + ppc_enable_pmcs(); /* set the freeze bit */ mmcr0 |= MMCR0_FC; |