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author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2021-04-08 18:30:26 +0300 |
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committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-04-14 16:04:18 +0300 |
commit | bf26e0bbd2f82b52605cd7c880245eefe67e09f3 (patch) | |
tree | b662e2020576bb117bfa266b869e1ea752719e31 /arch/powerpc/mm | |
parent | b26e8f27253a47bff90972b987112fd8396e9b8d (diff) | |
download | linux-bf26e0bbd2f82b52605cd7c880245eefe67e09f3.tar.xz |
powerpc/mem: Declare __flush_dcache_icache() static
__flush_dcache_icache() is only used in mem.c.
Move it before the functions that use it and declare it static.
And also fix the name of the parameter in the comment.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/3fa903eb5a10b2bc7d99a8c559ffdaa05452d8e0.1617895813.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r-- | arch/powerpc/mm/cacheflush.c | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/arch/powerpc/mm/cacheflush.c b/arch/powerpc/mm/cacheflush.c index 40613d2fda37..742d3e0fb12f 100644 --- a/arch/powerpc/mm/cacheflush.c +++ b/arch/powerpc/mm/cacheflush.c @@ -135,6 +135,36 @@ void flush_dcache_page(struct page *page) } EXPORT_SYMBOL(flush_dcache_page); +/** + * __flush_dcache_icache(): Flush a particular page from the data cache to RAM. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * + * @p: the address of the page to flush + */ +static void __flush_dcache_icache(void *p) +{ + unsigned long addr = (unsigned long)p; + + if (flush_coherent_icache(addr)) + return; + + clean_dcache_range(addr, addr + PAGE_SIZE); + + /* + * We don't flush the icache on 44x. Those have a virtual icache and we + * don't have access to the virtual address here (it's not the page + * vaddr but where it's mapped in user space). The flushing of the + * icache on these is handled elsewhere, when a change in the address + * space occurs, before returning to user space. + */ + + if (mmu_has_feature(MMU_FTR_TYPE_44x)) + return; + + invalidate_icache_range(addr, addr + PAGE_SIZE); +} + static void flush_dcache_icache_hugepage(struct page *page) { int i; @@ -178,36 +208,6 @@ void flush_dcache_icache_page(struct page *page) } EXPORT_SYMBOL(flush_dcache_icache_page); -/** - * __flush_dcache_icache(): Flush a particular page from the data cache to RAM. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * - * @page: the address of the page to flush - */ -void __flush_dcache_icache(void *p) -{ - unsigned long addr = (unsigned long)p; - - if (flush_coherent_icache(addr)) - return; - - clean_dcache_range(addr, addr + PAGE_SIZE); - - /* - * We don't flush the icache on 44x. Those have a virtual icache and we - * don't have access to the virtual address here (it's not the page - * vaddr but where it's mapped in user space). The flushing of the - * icache on these is handled elsewhere, when a change in the address - * space occurs, before returning to user space. - */ - - if (mmu_has_feature(MMU_FTR_TYPE_44x)) - return; - - invalidate_icache_range(addr, addr + PAGE_SIZE); -} - void clear_user_page(void *page, unsigned long vaddr, struct page *pg) { clear_page(page); |