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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2017-07-24 07:28:00 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2017-08-18 06:07:16 +0300
commit1a92a80ad386a1a6e3b36d576d52a1a456394b70 (patch)
tree7c23e2a850b9353cf6debd63dcde4c073b370f56 /arch/powerpc/kernel/idle_book3s.S
parent5a69aec945d27e78abac9fd032533d3aaebf7c1e (diff)
downloadlinux-1a92a80ad386a1a6e3b36d576d52a1a456394b70.tar.xz
powerpc/mm: Ensure cpumask update is ordered
There is no guarantee that the various isync's involved with the context switch will order the update of the CPU mask with the first TLB entry for the new context being loaded by the HW. Be safe here and add a memory barrier to order any subsequent load/store which may bring entries into the TLB. The corresponding barrier on the other side already exists as pte updates use pte_xchg() which uses __cmpxchg_u64 which has a sync after the atomic operation. Cc: stable@vger.kernel.org Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Add comments in the code] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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