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author | Mihai Caraman <mihai.caraman@freescale.com> | 2014-09-01 13:01:58 +0400 |
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committer | Alexander Graf <agraf@suse.de> | 2014-09-22 12:11:35 +0400 |
commit | 188e267ce249b491dfbb77d881996dcb5610dc90 (patch) | |
tree | c7d5c386562371f0e4dad2c3d885d9b2d58a3e6c /arch/powerpc/include/asm/kvm_booke.h | |
parent | 9333e6c4c15a4084dd5f4336cd4379afbf99e458 (diff) | |
download | linux-188e267ce249b491dfbb77d881996dcb5610dc90.tar.xz |
KVM: PPC: e500mc: Add support for single threaded vcpus on e6500 core
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional instruction, the Linux kernel uses per core mechanisms to
protect against duplicate TLB entries.
The guest is unable to detect real siblings threads, so it can't use the
TLB protection mechanism. An alternative solution is to use the hypervisor
to allocate different lpids to guest's vcpus that runs simultaneous on real
siblings threads. On systems with two threads per core this patch halves
the size of the lpid pool that the allocator sees and use two lpids per VM.
Use even numbers to speedup vcpu lpid computation with consecutive lpids
per VM: vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
[agraf: fix spelling]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/include/asm/kvm_booke.h')
-rw-r--r-- | arch/powerpc/include/asm/kvm_booke.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h index f7aa5cc395c4..630134d17f5d 100644 --- a/arch/powerpc/include/asm/kvm_booke.h +++ b/arch/powerpc/include/asm/kvm_booke.h @@ -23,7 +23,10 @@ #include <linux/types.h> #include <linux/kvm_host.h> -/* LPIDs we support with this build -- runtime limit may be lower */ +/* + * Number of available lpids. Only the low-order 6 bits of LPID rgister are + * implemented on e500mc+ cores. + */ #define KVMPPC_NR_LPIDS 64 #define KVMPPC_INST_EHPRIV 0x7c00021c |