diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2007-12-21 07:39:33 +0300 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-23 22:14:48 +0300 |
| commit | 190de005384204ba4dc339c3d05f8d40f6b16643 (patch) | |
| tree | 83fff853bdde49ec29e0fb488d8bf9578bec627a /arch/powerpc/boot/dcr.h | |
| parent | bc0b4e7ffb528282df5f8ba9c7c3f60135603e9e (diff) | |
| download | linux-190de005384204ba4dc339c3d05f8d40f6b16643.tar.xz | |
[POWERPC] 4xx: Rework clock probing in boot wrapper
This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.
Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case. Also handle the subtle difference
between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived
from the PLB clock while on the later, it's derived from the OPB.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
| -rw-r--r-- | arch/powerpc/boot/dcr.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index f6b793573b96..55655f78505a 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -160,6 +160,23 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, #define DCRN_CPR0_PERD 0x0e0 #define DCRN_CPR0_MALD 0x100 +#define DCRN_SDR0_CONFIG_ADDR 0xe +#define DCRN_SDR0_CONFIG_DATA 0xf + +/* SDR read/write helper macros */ +#define SDR0_READ(offset) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mfdcr(DCRN_SDR0_CONFIG_DATA); }) +#define SDR0_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mtdcr(DCRN_SDR0_CONFIG_DATA, data); }) + +#define DCRN_SDR0_UART0 0x0120 +#define DCRN_SDR0_UART1 0x0121 +#define DCRN_SDR0_UART2 0x0122 +#define DCRN_SDR0_UART3 0x0123 + + /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */ #define DCRN_CPR0_CFGADDR 0xc |