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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2015-11-21 17:29:47 +0300 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2015-11-25 03:02:23 +0300 |
| commit | f4ce7effe2253a325f8ba182903cbdf0d8698593 (patch) | |
| tree | e04fc670c53f3624222828354279c6ddb736b24d /arch/parisc | |
| parent | 937b12306ea79044c86f2e69b3061c7279245825 (diff) | |
| download | linux-f4ce7effe2253a325f8ba182903cbdf0d8698593.tar.xz | |
ARM: BCM5310X: activate erratas needed for SoC
The BCM4708 I have, which is probably the first generation which got
to the consumer market, is using a ARM Cortex-A9 rev r3p0 and a
L2C-310 rev r3p2 L2 cache controller. There are 3 workarounds for known
erratas in the Linux kernel which could be activated and will be in
this patch. There are currently no workarounds which have to be
activated for the L2C-310 rev r3p2 in Linux.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/parisc')
0 files changed, 0 insertions, 0 deletions