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author | Will Deacon <will.deacon@arm.com> | 2013-09-04 14:34:08 +0400 |
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committer | Will Deacon <will.deacon@arm.com> | 2014-10-20 21:49:18 +0400 |
commit | 2f083481cfd38320ebde0b83d836b967a2419d53 (patch) | |
tree | fc736d9067db7a55c448aced9a5630bdb1e85939 /arch/parisc | |
parent | 960a5597c39109ed2e12964cd9dc34857e5afee2 (diff) | |
download | linux-2f083481cfd38320ebde0b83d836b967a2419d53.tar.xz |
parisc: io: implement dummy relaxed accessor macros for writes
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to parisc, in the
same vein as the dummy definitions for the relaxed read accessors.
Cc: Helge Deller <deller@gmx.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/parisc')
-rw-r--r-- | arch/parisc/include/asm/io.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h index 1f6d2ae7aba5..8cd0abf28ffb 100644 --- a/arch/parisc/include/asm/io.h +++ b/arch/parisc/include/asm/io.h @@ -217,10 +217,14 @@ static inline void writeq(unsigned long long q, volatile void __iomem *addr) #define writel writel #define writeq writeq -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define readq_relaxed(addr) readq(addr) +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) +#define readq_relaxed(addr) readq(addr) +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(w, addr) writew(w, addr) +#define writel_relaxed(l, addr) writel(l, addr) +#define writeq_relaxed(q, addr) writeq(q, addr) #define mmiowb() do { } while (0) |