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| author | Siarhei Volkau <lis8215@gmail.com> | 2024-04-30 18:45:58 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-05-03 15:22:38 +0300 |
| commit | 07e6a6d7f1d9fa4685003a195032698ba99577bb (patch) | |
| tree | b165364619eff3753f7f3a7c11b681a9fae67176 /arch/mips | |
| parent | bfe4ab93c80cc5689ab5a891e61013dfec48f56e (diff) | |
| download | linux-07e6a6d7f1d9fa4685003a195032698ba99577bb.tar.xz | |
MIPS: Take in account load hazards for HI/LO restoring
MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load
and right after move to HI/LO will usually stall the pipeline for
significant amount of time. Let's take it into account and separate
loads and mthi/lo in instruction sequence.
The patch uses t6 and t7 registers as temporaries in addition to t8.
The patch tries to deal with SmartMIPS, but I know little about and
haven't tested it.
Changes in v2:
- clear separation of actions for SmartMIPS and pre-MIPSR6.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/stackframe.h | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a8705aef47e1..a13431379073 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -308,17 +308,12 @@ jal octeon_mult_restore #endif #ifdef CONFIG_CPU_HAS_SMARTMIPS - LONG_L $24, PT_ACX(sp) - mtlhx $24 - LONG_L $24, PT_HI(sp) - mtlhx $24 + LONG_L $14, PT_ACX(sp) LONG_L $24, PT_LO(sp) - mtlhx $24 + LONG_L $15, PT_HI(sp) #elif !defined(CONFIG_CPU_MIPSR6) LONG_L $24, PT_LO(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - mthi $24 + LONG_L $15, PT_HI(sp) #endif #ifdef CONFIG_32BIT cfi_ld $8, PT_R8, \docfi @@ -327,6 +322,14 @@ cfi_ld $10, PT_R10, \docfi cfi_ld $11, PT_R11, \docfi cfi_ld $12, PT_R12, \docfi +#ifdef CONFIG_CPU_HAS_SMARTMIPS + mtlhx $14 + mtlhx $15 + mtlhx $24 +#elif !defined(CONFIG_CPU_MIPSR6) + mtlo $24 + mthi $15 +#endif cfi_ld $13, PT_R13, \docfi cfi_ld $14, PT_R14, \docfi cfi_ld $15, PT_R15, \docfi |