diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-03-14 13:25:49 +0300 |
|---|---|---|
| committer | James Hogan <james.hogan@imgtec.com> | 2017-03-28 17:36:19 +0300 |
| commit | 3ba731daf09a2dd9515713e2428ef859bb50957b (patch) | |
| tree | 9b1918df19154d34de72f719b17065f50c3194e7 /arch/mips/kvm | |
| parent | 824533ad169f8bafcafba385a428e5b680928411 (diff) | |
| download | linux-3ba731daf09a2dd9515713e2428ef859bb50957b.tar.xz | |
KVM: MIPS/VZ: Emulate hit CACHE ops for Octeon III
Octeon III doesn't implement the optional GuestCtl0.CG bit to allow
guest mode to execute virtual address based CACHE instructions, so
implement emulation of a few important ones specifically for Octeon III
in response to a GPSI exception.
Currently the main reason to perform these operations is for icache
synchronisation, so they are implemented as a simple icache flush with
local_flush_icache_range().
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Diffstat (limited to 'arch/mips/kvm')
| -rw-r--r-- | arch/mips/kvm/vz.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 21f4495feb15..5c495277bf44 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -1105,6 +1105,17 @@ static enum emulation_result kvm_vz_gpsi_cache(union mips_instruction inst, case Index_Writeback_Inv_D: flush_dcache_line_indexed(va); return EMULATE_DONE; + case Hit_Invalidate_I: + case Hit_Invalidate_D: + case Hit_Writeback_Inv_D: + if (boot_cpu_type() == CPU_CAVIUM_OCTEON3) { + /* We can just flush entire icache */ + local_flush_icache_range(0, 0); + return EMULATE_DONE; + } + + /* So far, other platforms support guest hit cache ops */ + break; default: break; }; |