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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-11-13 19:13:18 +0300
committerRalf Baechle <ralf@linux-mips.org>2006-11-30 04:14:46 +0300
commit1417836e81c0ab8f5a0bfeafa90d3eaa41b2a067 (patch)
tree0274893cb78ca2e1bb85c3eee0c07a85e0b83d04 /arch/mips/kernel
parent1603b5aca4f15b34848fb5594d0c7b6333b99144 (diff)
downloadlinux-1417836e81c0ab8f5a0bfeafa90d3eaa41b2a067.tar.xz
[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/irq-msc01.c2
-rw-r--r--arch/mips/kernel/irq-mv6434x.c3
-rw-r--r--arch/mips/kernel/irq-rm7000.c3
-rw-r--r--arch/mips/kernel/irq-rm9000.c6
-rw-r--r--arch/mips/kernel/irq_cpu.c5
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smtc.c1
7 files changed, 17 insertions, 5 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index e1880b27381b..bcaad6696082 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -117,6 +117,7 @@ struct irq_chip msc_levelirq_type = {
.mask = mask_msc_irq,
.mask_ack = level_mask_and_ack_msc_irq,
.unmask = unmask_msc_irq,
+ .eoi = unmask_msc_irq,
.end = end_msc_irq,
};
@@ -126,6 +127,7 @@ struct irq_chip msc_edgeirq_type = {
.mask = mask_msc_irq,
.mask_ack = edge_mask_and_ack_msc_irq,
.unmask = unmask_msc_irq,
+ .eoi = unmask_msc_irq,
.end = end_msc_irq,
};
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 5012b9df1b5a..6cfb31cafde2 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -114,7 +114,8 @@ void __init mv64340_irq_init(unsigned int base)
int i;
for (i = base; i < base + 64; i++)
- set_irq_chip(i, &mv64340_irq_type);
+ set_irq_chip_and_handler(i, &mv64340_irq_type,
+ handle_level_irq);
irq_base = base;
}
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6a297e3b8899..ddcc2a5f8a06 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -51,7 +51,8 @@ void __init rm7k_cpu_irq_init(int base)
clear_c0_intcontrol(0x00000f00); /* Mask all */
for (i = base; i < base + 4; i++)
- set_irq_chip(i, &rm7k_irq_controller);
+ set_irq_chip_and_handler(i, &rm7k_irq_controller,
+ handle_level_irq);
irq_base = base;
}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 977538445cf3..ba6440c88abd 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -117,10 +117,12 @@ void __init rm9k_cpu_irq_init(int base)
clear_c0_intcontrol(0x0000f000); /* Mask all */
for (i = base; i < base + 4; i++)
- set_irq_chip(i, &rm9k_irq_controller);
+ set_irq_chip_and_handler(i, &rm9k_irq_controller,
+ handle_level_irq);
rm9000_perfcount_irq = base + 1;
- set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq);
+ set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
+ handle_level_irq);
irq_base = base;
}
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 3b7cfa407e87..be5ac23d3812 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -62,6 +62,7 @@ static struct irq_chip mips_cpu_irq_controller = {
.mask = mask_mips_irq,
.mask_ack = mask_mips_irq,
.unmask = unmask_mips_irq,
+ .eoi = unmask_mips_irq,
.end = mips_cpu_irq_end,
};
@@ -104,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
.mask = mask_mips_mt_irq,
.mask_ack = mips_mt_cpu_irq_ack,
.unmask = unmask_mips_mt_irq,
+ .eoi = unmask_mips_mt_irq,
.end = mips_mt_cpu_irq_end,
};
@@ -124,7 +126,8 @@ void __init mips_cpu_irq_init(int irq_base)
set_irq_chip(i, &mips_mt_cpu_irq_controller);
for (i = irq_base + 2; i < irq_base + 8; i++)
- set_irq_chip(i, &mips_cpu_irq_controller);
+ set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
+ handle_level_irq);
mips_cpu_irq_base = irq_base;
}
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2ac19a6cbf68..1ee689c0e0c9 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
/* need to mark IPI's as IRQ_PER_CPU */
irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
+ set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
+ set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
}
/*
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 3b78caf112f5..802febed7df5 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void)
setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
+ set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
}
/*