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authorRalf Baechle <ralf@linux-mips.org>2015-06-09 16:04:38 +0300
committerRalf Baechle <ralf@linux-mips.org>2015-06-21 22:54:31 +0300
commitcb2224d7c40e3d2dfc6f4a1676cd817acc79f012 (patch)
tree7ef2588fb1835b73bd0077958986acad0eb60e02 /arch/mips/kernel/irq.c
parent6f6ed482653723e53da4a57b200348ac1eed5ce9 (diff)
downloadlinux-cb2224d7c40e3d2dfc6f4a1676cd817acc79f012.tar.xz
MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
allocate_irqno, free_irqno and alloc_legacy_irqno are a simple allocator for interrupt numbers from the days when the numer of interrupts was still fixed to NR_IRQS. This was necessary for the SGI IP27 architecture which with its flexible architecture and possibly large number of interrupts doesn't easily fit into the old pattern. These days there are better alternatives. Move the allocation code from the arch generic code to the only platform using it, the SGI IP27 aka Origin 200/2000, Onyx 2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq.c')
-rw-r--r--arch/mips/kernel/irq.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index c3d831a8c479..8eb5af805964 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -25,44 +25,6 @@
#include <linux/atomic.h>
#include <asm/uaccess.h>
-static DECLARE_BITMAP(irq_map, NR_IRQS);
-
-int allocate_irqno(void)
-{
- int irq;
-
-again:
- irq = find_first_zero_bit(irq_map, NR_IRQS);
-
- if (irq >= NR_IRQS)
- return -ENOSPC;
-
- if (test_and_set_bit(irq, irq_map))
- goto again;
-
- return irq;
-}
-
-/*
- * Allocate the 16 legacy interrupts for i8259 devices. This happens early
- * in the kernel initialization so treating allocation failure as BUG() is
- * ok.
- */
-void __init alloc_legacy_irqno(void)
-{
- int i;
-
- for (i = 0; i <= 16; i++)
- BUG_ON(test_and_set_bit(i, irq_map));
-}
-
-void free_irqno(unsigned int irq)
-{
- smp_mb__before_atomic();
- clear_bit(irq, irq_map);
- smp_mb__after_atomic();
-}
-
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
* each architecture has to answer this themselves.