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authorDavid Daney <david.daney@cavium.com>2014-05-29 01:52:04 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-05-30 23:01:09 +0400
commita36d8225bceba4b7be47ade34d175945f85cffbc (patch)
treee410a514298003ab96d3a10cf091c518a8a423c8 /arch/mips/kernel/branch.c
parentdadaa1c2c0eddc09d11d7494b040c3f331ecd98f (diff)
downloadlinux-a36d8225bceba4b7be47ade34d175945f85cffbc.tar.xz
MIPS: OCTEON: Enable use of FPU
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/branch.c')
-rw-r--r--arch/mips/kernel/branch.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 84888d9332b9..e198d9bf17bb 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -562,7 +562,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case cop1_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();