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authorMarkos Chandras <markos.chandras@imgtec.com>2014-11-13 16:25:51 +0300
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 18:37:20 +0300
commit934c79231c1b3a88ed1ef8f1473fb26849ae501c (patch)
tree236efbdff02a3033cc90e8308e7cbb87821e8f23 /arch/mips/kernel/Makefile
parent8716a7635665008291d3f19dd5d36a858ed1561b (diff)
downloadlinux-934c79231c1b3a88ed1ef8f1473fb26849ae501c.tar.xz
MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions
MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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