MIPS: Fix build warning about "PTR_STR" redefinition

PTR_STR is redefined when CONFIG_TEST_PRINTF is set. This causes the
following build warning:

  CC      lib/test_printf.o
lib/test_printf.c:214:0: warning: "PTR_STR" redefined
 #define PTR_STR "ffff0123456789ab"
 ^
In file included from ./arch/mips/include/asm/dsemul.h:11:0,
                 from ./arch/mips/include/asm/processor.h:22,
                 from ./arch/mips/include/asm/thread_info.h:16,
                 from ./include/linux/thread_info.h:38,
                 from ./include/asm-generic/preempt.h:5,
                 from ./arch/mips/include/generated/asm/preempt.h:1,
                 from ./include/linux/preempt.h:78,
                 from ./include/linux/spinlock.h:51,
                 from ./include/linux/seqlock.h:36,
                 from ./include/linux/time.h:6,
                 from ./include/linux/stat.h:19,
                 from ./include/linux/module.h:13,
                 from lib/test_printf.c:10:
./arch/mips/include/asm/inst.h:20:0: note: this is the location of the previous definition
 #define PTR_STR  ".dword"
 ^

Instead of renaming PTR_STR we move the unaligned macros to a new file,
which is only included inside MIPS code. This way we can safely include
asm.h and can use STR(PTR) again.

Fixes: e701656ec4db ("MIPS: inst.h: Stop including asm.h to avoid various build failures")
Cc: Maciej W. Rozycki" <macro@linux-mips.org>
Reported-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

2 files changed, 779 insertions, 779 deletions

diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6d74ba33b923..22912f78401c 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -13,13 +13,6 @@
 
 #include <uapi/asm/inst.h>
 
-#if (_MIPS_SZPTR == 32)
-#define PTR_STR		".word"
-#endif
-#if (_MIPS_SZPTR == 64)
-#define PTR_STR		".dword"
-#endif
-
 /* HACHACHAHCAHC ...  */
 
 /* In case some other massaging is needed, keep MIPSInst as wrapper */
@@ -92,776 +85,4 @@ struct mm_decoded_insn {
 /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
 extern const int reg16to32[];
 
-#ifdef __BIG_ENDIAN
-#define  _LoadHW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (".set\tnoat\n"        \
-		"1:\t"type##_lb("%0", "0(%2)")"\n"  \
-		"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
-		"sll\t%0, 0x8\n\t"                  \
-		"or\t%0, $1\n\t"                    \
-		"li\t%1, 0\n"                       \
-		"3:\t.set\tat\n\t"                  \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _LoadW(addr, value, res, type)   \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_lwl("%0", "(%2)")"\n"   \
-		"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-/* For CPUs without lwl instruction */
-#define  _LoadW(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n"			    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_lb("%0", "0(%2)")"\n\t"  \
-		"2:"type##_lbu("$1", "1(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:"type##_lbu("$1", "2(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:"type##_lbu("$1", "3(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-
-#define  _LoadHWU(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tnoat\n"                      \
-		"1:\t"type##_lbu("%0", "0(%2)")"\n" \
-		"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
-		"sll\t%0, 0x8\n\t"                  \
-		"or\t%0, $1\n\t"                    \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".set\tat\n\t"                      \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _LoadWU(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_lwl("%0", "(%2)")"\n"  \
-		"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
-		"dsll\t%0, %0, 32\n\t"              \
-		"dsrl\t%0, %0, 32\n\t"              \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		"\t.section\t.fixup,\"ax\"\n\t"     \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#define  _LoadDW(addr, value, res)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\tldl\t%0, (%2)\n"               \
-		"2:\tldr\t%0, 7(%2)\n\t"            \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		"\t.section\t.fixup,\"ax\"\n\t"     \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-/* For CPUs without lwl and ldl instructions */
-#define  _LoadWU(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_lbu("%0", "0(%2)")"\n\t" \
-		"2:"type##_lbu("$1", "1(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:"type##_lbu("$1", "2(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:"type##_lbu("$1", "3(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#define  _LoadDW(addr, value, res)  \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:lb\t%0, 0(%2)\n\t"		    \
-		"2:lbu\t $1, 1(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:lbu\t$1, 2(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:lbu\t$1, 3(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"5:lbu\t$1, 4(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"6:lbu\t$1, 5(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"7:lbu\t$1, 6(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"8:lbu\t$1, 7(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n\t"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		PTR_STR"\t5b, 11b\n\t"		    \
-		PTR_STR"\t6b, 11b\n\t"		    \
-		PTR_STR"\t7b, 11b\n\t"		    \
-		PTR_STR"\t8b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-
-
-#define  _StoreHW(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tnoat\n"                      \
-		"1:\t"type##_sb("%1", "1(%2)")"\n"  \
-		"srl\t$1, %1, 0x8\n"                \
-		"2:\t"type##_sb("$1", "0(%2)")"\n"  \
-		".set\tat\n\t"                      \
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"              \
-		PTR_STR"\t2b, 4b\n\t"              \
-		".previous"                         \
-		: "=r" (res)                        \
-		: "r" (value), "r" (addr), "i" (-EFAULT));\
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _StoreW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_swl("%1", "(%2)")"\n"  \
-		"2:\t"type##_swr("%1", "3(%2)")"\n\t"\
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=r" (res)                                \
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
-} while (0)
-
-#define  _StoreDW(addr, value, res) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\tsdl\t%1,(%2)\n"                \
-		"2:\tsdr\t%1, 7(%2)\n\t"            \
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=r" (res)                                \
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-#define  _StoreW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_sb("%1", "3(%2)")"\n\t"  \
-		"srl\t$1, %1, 0x8\n\t"		    \
-		"2:"type##_sb("$1", "2(%2)")"\n\t"  \
-		"srl\t$1, $1,  0x8\n\t"		    \
-		"3:"type##_sb("$1", "1(%2)")"\n\t"  \
-		"srl\t$1, $1, 0x8\n\t"		    \
-		"4:"type##_sb("$1", "0(%2)")"\n\t"  \
-		".set\tpop\n\t"			    \
-		"li\t%0, 0\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%0, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (res)				    \
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
-		: "memory");                                \
-} while (0)
-
-#define  _StoreDW(addr, value, res) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:sb\t%1, 7(%2)\n\t"		    \
-		"dsrl\t$1, %1, 0x8\n\t"		    \
-		"2:sb\t$1, 6(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"3:sb\t$1, 5(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"4:sb\t$1, 4(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"5:sb\t$1, 3(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"6:sb\t$1, 2(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"7:sb\t$1, 1(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"8:sb\t$1, 0(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		".set\tpop\n\t"			    \
-		"li\t%0, 0\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%0, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		PTR_STR"\t5b, 11b\n\t"		    \
-		PTR_STR"\t6b, 11b\n\t"		    \
-		PTR_STR"\t7b, 11b\n\t"		    \
-		PTR_STR"\t8b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (res)				    \
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
-		: "memory");                                \
-} while (0)
-
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-
-#else /* __BIG_ENDIAN */
-
-#define  _LoadHW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (".set\tnoat\n"        \
-		"1:\t"type##_lb("%0", "1(%2)")"\n"  \
-		"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
-		"sll\t%0, 0x8\n\t"                  \
-		"or\t%0, $1\n\t"                    \
-		"li\t%1, 0\n"                       \
-		"3:\t.set\tat\n\t"                  \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _LoadW(addr, value, res, type)   \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_lwl("%0", "3(%2)")"\n" \
-		"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-/* For CPUs without lwl instruction */
-#define  _LoadW(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n"			    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_lb("%0", "3(%2)")"\n\t"  \
-		"2:"type##_lbu("$1", "2(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:"type##_lbu("$1", "1(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:"type##_lbu("$1", "0(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-
-
-#define  _LoadHWU(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tnoat\n"                      \
-		"1:\t"type##_lbu("%0", "1(%2)")"\n" \
-		"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
-		"sll\t%0, 0x8\n\t"                  \
-		"or\t%0, $1\n\t"                    \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".set\tat\n\t"                      \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _LoadWU(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_lwl("%0", "3(%2)")"\n" \
-		"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
-		"dsll\t%0, %0, 32\n\t"              \
-		"dsrl\t%0, %0, 32\n\t"              \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		"\t.section\t.fixup,\"ax\"\n\t"     \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#define  _LoadDW(addr, value, res)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\tldl\t%0, 7(%2)\n"              \
-		"2:\tldr\t%0, (%2)\n\t"             \
-		"li\t%1, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		"\t.section\t.fixup,\"ax\"\n\t"     \
-		"4:\tli\t%1, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=&r" (value), "=r" (res)         \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-/* For CPUs without lwl and ldl instructions */
-#define  _LoadWU(addr, value, res, type) \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_lbu("%0", "3(%2)")"\n\t" \
-		"2:"type##_lbu("$1", "2(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:"type##_lbu("$1", "1(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:"type##_lbu("$1", "0(%2)")"\n\t" \
-		"sll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-
-#define  _LoadDW(addr, value, res)  \
-do {                                                \
-	__asm__ __volatile__ (			    \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:lb\t%0, 7(%2)\n\t"		    \
-		"2:lbu\t$1, 6(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"3:lbu\t$1, 5(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"4:lbu\t$1, 4(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"5:lbu\t$1, 3(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"6:lbu\t$1, 2(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"7:lbu\t$1, 1(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"8:lbu\t$1, 0(%2)\n\t"		    \
-		"dsll\t%0, 0x8\n\t"		    \
-		"or\t%0, $1\n\t"		    \
-		"li\t%1, 0\n"			    \
-		".set\tpop\n\t"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%1, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		PTR_STR"\t5b, 11b\n\t"		    \
-		PTR_STR"\t6b, 11b\n\t"		    \
-		PTR_STR"\t7b, 11b\n\t"		    \
-		PTR_STR"\t8b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (value), "=r" (res)	    \
-		: "r" (addr), "i" (-EFAULT));       \
-} while (0)
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-
-#define  _StoreHW(addr, value, res, type) \
-do {                                                 \
-	__asm__ __volatile__ (                      \
-		".set\tnoat\n"                      \
-		"1:\t"type##_sb("%1", "0(%2)")"\n"  \
-		"srl\t$1,%1, 0x8\n"                 \
-		"2:\t"type##_sb("$1", "1(%2)")"\n"  \
-		".set\tat\n\t"                      \
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=r" (res)                        \
-		: "r" (value), "r" (addr), "i" (-EFAULT));\
-} while (0)
-
-#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
-#define  _StoreW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\t"type##_swl("%1", "3(%2)")"\n" \
-		"2:\t"type##_swr("%1", "(%2)")"\n\t"\
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=r" (res)                                \
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
-} while (0)
-
-#define  _StoreDW(addr, value, res) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		"1:\tsdl\t%1, 7(%2)\n"              \
-		"2:\tsdr\t%1, (%2)\n\t"             \
-		"li\t%0, 0\n"                       \
-		"3:\n\t"                            \
-		".insn\n\t"                         \
-		".section\t.fixup,\"ax\"\n\t"       \
-		"4:\tli\t%0, %3\n\t"                \
-		"j\t3b\n\t"                         \
-		".previous\n\t"                     \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 4b\n\t"               \
-		PTR_STR"\t2b, 4b\n\t"               \
-		".previous"                         \
-		: "=r" (res)                                \
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
-} while (0)
-
-#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
-/* For CPUs without swl and sdl instructions */
-#define  _StoreW(addr, value, res, type)  \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:"type##_sb("%1", "0(%2)")"\n\t"  \
-		"srl\t$1, %1, 0x8\n\t"		    \
-		"2:"type##_sb("$1", "1(%2)")"\n\t"  \
-		"srl\t$1, $1,  0x8\n\t"		    \
-		"3:"type##_sb("$1", "2(%2)")"\n\t"  \
-		"srl\t$1, $1, 0x8\n\t"		    \
-		"4:"type##_sb("$1", "3(%2)")"\n\t"  \
-		".set\tpop\n\t"			    \
-		"li\t%0, 0\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%0, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (res)				    \
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
-		: "memory");                                \
-} while (0)
-
-#define  _StoreDW(addr, value, res) \
-do {                                                \
-	__asm__ __volatile__ (                      \
-		".set\tpush\n\t"		    \
-		".set\tnoat\n\t"		    \
-		"1:sb\t%1, 0(%2)\n\t"		    \
-		"dsrl\t$1, %1, 0x8\n\t"		    \
-		"2:sb\t$1, 1(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"3:sb\t$1, 2(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"4:sb\t$1, 3(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"5:sb\t$1, 4(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"6:sb\t$1, 5(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"7:sb\t$1, 6(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		"8:sb\t$1, 7(%2)\n\t"		    \
-		"dsrl\t$1, $1, 0x8\n\t"		    \
-		".set\tpop\n\t"			    \
-		"li\t%0, 0\n"			    \
-		"10:\n\t"			    \
-		".insn\n\t"			    \
-		".section\t.fixup,\"ax\"\n\t"	    \
-		"11:\tli\t%0, %3\n\t"		    \
-		"j\t10b\n\t"			    \
-		".previous\n\t"			    \
-		".section\t__ex_table,\"a\"\n\t"    \
-		PTR_STR"\t1b, 11b\n\t"		    \
-		PTR_STR"\t2b, 11b\n\t"		    \
-		PTR_STR"\t3b, 11b\n\t"		    \
-		PTR_STR"\t4b, 11b\n\t"		    \
-		PTR_STR"\t5b, 11b\n\t"		    \
-		PTR_STR"\t6b, 11b\n\t"		    \
-		PTR_STR"\t7b, 11b\n\t"		    \
-		PTR_STR"\t8b, 11b\n\t"		    \
-		".previous"			    \
-		: "=&r" (res)				    \
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
-		: "memory");                                \
-} while (0)
-
-#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
-#endif
-
-#define LoadHWU(addr, value, res)	_LoadHWU(addr, value, res, kernel)
-#define LoadHWUE(addr, value, res)	_LoadHWU(addr, value, res, user)
-#define LoadWU(addr, value, res)	_LoadWU(addr, value, res, kernel)
-#define LoadWUE(addr, value, res)	_LoadWU(addr, value, res, user)
-#define LoadHW(addr, value, res)	_LoadHW(addr, value, res, kernel)
-#define LoadHWE(addr, value, res)	_LoadHW(addr, value, res, user)
-#define LoadW(addr, value, res)		_LoadW(addr, value, res, kernel)
-#define LoadWE(addr, value, res)	_LoadW(addr, value, res, user)
-#define LoadDW(addr, value, res)	_LoadDW(addr, value, res)
-
-#define StoreHW(addr, value, res)	_StoreHW(addr, value, res, kernel)
-#define StoreHWE(addr, value, res)	_StoreHW(addr, value, res, user)
-#define StoreW(addr, value, res)	_StoreW(addr, value, res, kernel)
-#define StoreWE(addr, value, res)	_StoreW(addr, value, res, user)
-#define StoreDW(addr, value, res)	_StoreDW(addr, value, res)
-
 #endif /* _ASM_INST_H */
diff --git a/arch/mips/include/asm/unaligned-emul.h b/arch/mips/include/asm/unaligned-emul.h
new file mode 100644
index 000000000000..2022b18944b9
--- /dev/null
+++ b/arch/mips/include/asm/unaligned-emul.h
@@ -0,0 +1,779 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef _ASM_MIPS_UNALIGNED_EMUL_H
+#define _ASM_MIPS_UNALIGNED_EMUL_H
+
+#include <asm/asm.h>
+
+#ifdef __BIG_ENDIAN
+#define  _LoadHW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (".set\tnoat\n"        \
+		"1:\t"type##_lb("%0", "0(%2)")"\n"  \
+		"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
+		"sll\t%0, 0x8\n\t"                  \
+		"or\t%0, $1\n\t"                    \
+		"li\t%1, 0\n"                       \
+		"3:\t.set\tat\n\t"                  \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadW(addr, value, res, type)   \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_lwl("%0", "(%2)")"\n"   \
+		"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl instruction */
+#define  _LoadW(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n"			    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_lb("%0", "0(%2)")"\n\t"  \
+		"2:"type##_lbu("$1", "1(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:"type##_lbu("$1", "2(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:"type##_lbu("$1", "3(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#define  _LoadHWU(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tnoat\n"                      \
+		"1:\t"type##_lbu("%0", "0(%2)")"\n" \
+		"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
+		"sll\t%0, 0x8\n\t"                  \
+		"or\t%0, $1\n\t"                    \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".set\tat\n\t"                      \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadWU(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_lwl("%0", "(%2)")"\n"  \
+		"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
+		"dsll\t%0, %0, 32\n\t"              \
+		"dsrl\t%0, %0, 32\n\t"              \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		"\t.section\t.fixup,\"ax\"\n\t"     \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\tldl\t%0, (%2)\n"               \
+		"2:\tldr\t%0, 7(%2)\n\t"            \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		"\t.section\t.fixup,\"ax\"\n\t"     \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl and ldl instructions */
+#define  _LoadWU(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_lbu("%0", "0(%2)")"\n\t" \
+		"2:"type##_lbu("$1", "1(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:"type##_lbu("$1", "2(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:"type##_lbu("$1", "3(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:lb\t%0, 0(%2)\n\t"		    \
+		"2:lbu\t $1, 1(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:lbu\t$1, 2(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:lbu\t$1, 3(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"5:lbu\t$1, 4(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"6:lbu\t$1, 5(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"7:lbu\t$1, 6(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"8:lbu\t$1, 7(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n\t"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		STR(PTR)"\t5b, 11b\n\t"		    \
+		STR(PTR)"\t6b, 11b\n\t"		    \
+		STR(PTR)"\t7b, 11b\n\t"		    \
+		STR(PTR)"\t8b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+
+#define  _StoreHW(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tnoat\n"                      \
+		"1:\t"type##_sb("%1", "1(%2)")"\n"  \
+		"srl\t$1, %1, 0x8\n"                \
+		"2:\t"type##_sb("$1", "0(%2)")"\n"  \
+		".set\tat\n\t"                      \
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"              \
+		STR(PTR)"\t2b, 4b\n\t"              \
+		".previous"                         \
+		: "=r" (res)                        \
+		: "r" (value), "r" (addr), "i" (-EFAULT));\
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_swl("%1", "(%2)")"\n"  \
+		"2:\t"type##_swr("%1", "3(%2)")"\n\t"\
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=r" (res)                                \
+		: "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\tsdl\t%1,(%2)\n"                \
+		"2:\tsdr\t%1, 7(%2)\n\t"            \
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=r" (res)                                \
+		: "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_sb("%1", "3(%2)")"\n\t"  \
+		"srl\t$1, %1, 0x8\n\t"		    \
+		"2:"type##_sb("$1", "2(%2)")"\n\t"  \
+		"srl\t$1, $1,  0x8\n\t"		    \
+		"3:"type##_sb("$1", "1(%2)")"\n\t"  \
+		"srl\t$1, $1, 0x8\n\t"		    \
+		"4:"type##_sb("$1", "0(%2)")"\n\t"  \
+		".set\tpop\n\t"			    \
+		"li\t%0, 0\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%0, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (res)				    \
+		: "r" (value), "r" (addr), "i" (-EFAULT)    \
+		: "memory");                                \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:sb\t%1, 7(%2)\n\t"		    \
+		"dsrl\t$1, %1, 0x8\n\t"		    \
+		"2:sb\t$1, 6(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"3:sb\t$1, 5(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"4:sb\t$1, 4(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"5:sb\t$1, 3(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"6:sb\t$1, 2(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"7:sb\t$1, 1(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"8:sb\t$1, 0(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		".set\tpop\n\t"			    \
+		"li\t%0, 0\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%0, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		STR(PTR)"\t5b, 11b\n\t"		    \
+		STR(PTR)"\t6b, 11b\n\t"		    \
+		STR(PTR)"\t7b, 11b\n\t"		    \
+		STR(PTR)"\t8b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (res)				    \
+		: "r" (value), "r" (addr), "i" (-EFAULT)    \
+		: "memory");                                \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#else /* __BIG_ENDIAN */
+
+#define  _LoadHW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (".set\tnoat\n"        \
+		"1:\t"type##_lb("%0", "1(%2)")"\n"  \
+		"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
+		"sll\t%0, 0x8\n\t"                  \
+		"or\t%0, $1\n\t"                    \
+		"li\t%1, 0\n"                       \
+		"3:\t.set\tat\n\t"                  \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadW(addr, value, res, type)   \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_lwl("%0", "3(%2)")"\n" \
+		"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl instruction */
+#define  _LoadW(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n"			    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_lb("%0", "3(%2)")"\n\t"  \
+		"2:"type##_lbu("$1", "2(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:"type##_lbu("$1", "1(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:"type##_lbu("$1", "0(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+
+#define  _LoadHWU(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tnoat\n"                      \
+		"1:\t"type##_lbu("%0", "1(%2)")"\n" \
+		"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
+		"sll\t%0, 0x8\n\t"                  \
+		"or\t%0, $1\n\t"                    \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".set\tat\n\t"                      \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _LoadWU(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_lwl("%0", "3(%2)")"\n" \
+		"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
+		"dsll\t%0, %0, 32\n\t"              \
+		"dsrl\t%0, %0, 32\n\t"              \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		"\t.section\t.fixup,\"ax\"\n\t"     \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\tldl\t%0, 7(%2)\n"              \
+		"2:\tldr\t%0, (%2)\n\t"             \
+		"li\t%1, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		"\t.section\t.fixup,\"ax\"\n\t"     \
+		"4:\tli\t%1, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=&r" (value), "=r" (res)         \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without lwl and ldl instructions */
+#define  _LoadWU(addr, value, res, type) \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_lbu("%0", "3(%2)")"\n\t" \
+		"2:"type##_lbu("$1", "2(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:"type##_lbu("$1", "1(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:"type##_lbu("$1", "0(%2)")"\n\t" \
+		"sll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+
+#define  _LoadDW(addr, value, res)  \
+do {                                                \
+	__asm__ __volatile__ (			    \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:lb\t%0, 7(%2)\n\t"		    \
+		"2:lbu\t$1, 6(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"3:lbu\t$1, 5(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"4:lbu\t$1, 4(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"5:lbu\t$1, 3(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"6:lbu\t$1, 2(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"7:lbu\t$1, 1(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"8:lbu\t$1, 0(%2)\n\t"		    \
+		"dsll\t%0, 0x8\n\t"		    \
+		"or\t%0, $1\n\t"		    \
+		"li\t%1, 0\n"			    \
+		".set\tpop\n\t"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%1, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		STR(PTR)"\t5b, 11b\n\t"		    \
+		STR(PTR)"\t6b, 11b\n\t"		    \
+		STR(PTR)"\t7b, 11b\n\t"		    \
+		STR(PTR)"\t8b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (value), "=r" (res)	    \
+		: "r" (addr), "i" (-EFAULT));       \
+} while (0)
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+
+#define  _StoreHW(addr, value, res, type) \
+do {                                                 \
+	__asm__ __volatile__ (                      \
+		".set\tnoat\n"                      \
+		"1:\t"type##_sb("%1", "0(%2)")"\n"  \
+		"srl\t$1,%1, 0x8\n"                 \
+		"2:\t"type##_sb("$1", "1(%2)")"\n"  \
+		".set\tat\n\t"                      \
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=r" (res)                        \
+		: "r" (value), "r" (addr), "i" (-EFAULT));\
+} while (0)
+
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\t"type##_swl("%1", "3(%2)")"\n" \
+		"2:\t"type##_swr("%1", "(%2)")"\n\t"\
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=r" (res)                                \
+		: "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		"1:\tsdl\t%1, 7(%2)\n"              \
+		"2:\tsdr\t%1, (%2)\n\t"             \
+		"li\t%0, 0\n"                       \
+		"3:\n\t"                            \
+		".insn\n\t"                         \
+		".section\t.fixup,\"ax\"\n\t"       \
+		"4:\tli\t%0, %3\n\t"                \
+		"j\t3b\n\t"                         \
+		".previous\n\t"                     \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 4b\n\t"               \
+		STR(PTR)"\t2b, 4b\n\t"               \
+		".previous"                         \
+		: "=r" (res)                                \
+		: "r" (value), "r" (addr), "i" (-EFAULT));  \
+} while (0)
+
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
+/* For CPUs without swl and sdl instructions */
+#define  _StoreW(addr, value, res, type)  \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:"type##_sb("%1", "0(%2)")"\n\t"  \
+		"srl\t$1, %1, 0x8\n\t"		    \
+		"2:"type##_sb("$1", "1(%2)")"\n\t"  \
+		"srl\t$1, $1,  0x8\n\t"		    \
+		"3:"type##_sb("$1", "2(%2)")"\n\t"  \
+		"srl\t$1, $1, 0x8\n\t"		    \
+		"4:"type##_sb("$1", "3(%2)")"\n\t"  \
+		".set\tpop\n\t"			    \
+		"li\t%0, 0\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%0, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (res)				    \
+		: "r" (value), "r" (addr), "i" (-EFAULT)    \
+		: "memory");                                \
+} while (0)
+
+#define  _StoreDW(addr, value, res) \
+do {                                                \
+	__asm__ __volatile__ (                      \
+		".set\tpush\n\t"		    \
+		".set\tnoat\n\t"		    \
+		"1:sb\t%1, 0(%2)\n\t"		    \
+		"dsrl\t$1, %1, 0x8\n\t"		    \
+		"2:sb\t$1, 1(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"3:sb\t$1, 2(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"4:sb\t$1, 3(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"5:sb\t$1, 4(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"6:sb\t$1, 5(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"7:sb\t$1, 6(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		"8:sb\t$1, 7(%2)\n\t"		    \
+		"dsrl\t$1, $1, 0x8\n\t"		    \
+		".set\tpop\n\t"			    \
+		"li\t%0, 0\n"			    \
+		"10:\n\t"			    \
+		".insn\n\t"			    \
+		".section\t.fixup,\"ax\"\n\t"	    \
+		"11:\tli\t%0, %3\n\t"		    \
+		"j\t10b\n\t"			    \
+		".previous\n\t"			    \
+		".section\t__ex_table,\"a\"\n\t"    \
+		STR(PTR)"\t1b, 11b\n\t"		    \
+		STR(PTR)"\t2b, 11b\n\t"		    \
+		STR(PTR)"\t3b, 11b\n\t"		    \
+		STR(PTR)"\t4b, 11b\n\t"		    \
+		STR(PTR)"\t5b, 11b\n\t"		    \
+		STR(PTR)"\t6b, 11b\n\t"		    \
+		STR(PTR)"\t7b, 11b\n\t"		    \
+		STR(PTR)"\t8b, 11b\n\t"		    \
+		".previous"			    \
+		: "=&r" (res)				    \
+		: "r" (value), "r" (addr), "i" (-EFAULT)    \
+		: "memory");                                \
+} while (0)
+
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
+#endif
+
+#define LoadHWU(addr, value, res)	_LoadHWU(addr, value, res, kernel)
+#define LoadHWUE(addr, value, res)	_LoadHWU(addr, value, res, user)
+#define LoadWU(addr, value, res)	_LoadWU(addr, value, res, kernel)
+#define LoadWUE(addr, value, res)	_LoadWU(addr, value, res, user)
+#define LoadHW(addr, value, res)	_LoadHW(addr, value, res, kernel)
+#define LoadHWE(addr, value, res)	_LoadHW(addr, value, res, user)
+#define LoadW(addr, value, res)		_LoadW(addr, value, res, kernel)
+#define LoadWE(addr, value, res)	_LoadW(addr, value, res, user)
+#define LoadDW(addr, value, res)	_LoadDW(addr, value, res)
+
+#define StoreHW(addr, value, res)	_StoreHW(addr, value, res, kernel)
+#define StoreHWE(addr, value, res)	_StoreHW(addr, value, res, user)
+#define StoreW(addr, value, res)	_StoreW(addr, value, res, kernel)
+#define StoreWE(addr, value, res)	_StoreW(addr, value, res, user)
+#define StoreDW(addr, value, res)	_StoreDW(addr, value, res)
+
+#endif /* _ASM_MIPS_UNALIGNED_EMUL_H */