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| author | Paul Burton <paul.burton@imgtec.com> | 2014-07-30 11:53:20 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-08-02 02:06:44 +0400 |
| commit | c9017757c532d48bf43d6e7d3b7282443ad4207b (patch) | |
| tree | 169346d3830d35c20c8cce14cb9c91cb3bfc3b7a /arch/mips/include/asm/msa.h | |
| parent | 33c771ba5c5d067f85a5a6c4b11047219b5b8f4e (diff) | |
| download | linux-c9017757c532d48bf43d6e7d3b7282443ad4207b.tar.xz | |
MIPS: init upper 64b of vector registers when MSA is first used
When a task first makes use of MSA we need to ensure that the upper
64b of the vector registers are set to some value such that no
information can be leaked to it from the previous task to use MSA
context on the CPU. The architecture formerly specified that these
bits would be cleared to 0 when a scalar FP instructions wrote to the
aliased FP registers, which would have implicitly handled this as the
kernel restored scalar FP context. However more recent versions of the
specification now state that the value of the bits in such cases is
unpredictable. Initialise them explictly to be sure, and set all the
bits to 1 rather than 0 for consistency with the least significant
64b.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7497/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/msa.h')
| -rw-r--r-- | arch/mips/include/asm/msa.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index e80e85c1334f..fe25a17bc783 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -16,6 +16,7 @@ extern void _save_msa(struct task_struct *); extern void _restore_msa(struct task_struct *); +extern void _init_msa_upper(void); static inline void enable_msa(void) { |