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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 19:32:44 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 23:23:38 +0300 |
| commit | 5e5b6527128cea50f12a7064bf61b130b3a2739a (patch) | |
| tree | 6dcaaf2a258785705bacc2447f4f639f575aa4c6 /arch/mips/include/asm/mach-sibyte | |
| parent | 802b83627f54d63d3d95d0285ec9a5d80be434c0 (diff) | |
| download | linux-5e5b6527128cea50f12a7064bf61b130b3a2739a.tar.xz | |
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-sibyte')
| -rw-r--r-- | arch/mips/include/asm/mach-sibyte/war.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index d34f3c1d6741..bf793d36c890 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H #define __ASM_MIPS_MACH_SIBYTE_WAR_H -#define R4600_V1_HIT_CACHEOP_WAR 0 #define R4600_V2_HIT_CACHEOP_WAR 0 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS) |