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authorSteven J. Hill <sjhill@mips.com>2012-05-31 01:02:49 +0400
committerSteven J. Hill <sjhill@mips.com>2012-09-14 00:43:46 +0400
commit3070033a16edcc21688d5ea8967c89522f833862 (patch)
tree48d1a4601dd4750d103bc0b02ff2494d75220321 /arch/mips/include/asm/mach-sead3/war.h
parent006a851b10a395955c153a145ad8241494d43688 (diff)
downloadlinux-3070033a16edcc21688d5ea8967c89522f833862.tar.xz
MIPS: Add core files for MIPS SEAD-3 development platform.
More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'arch/mips/include/asm/mach-sead3/war.h')
-rw-r--r--arch/mips/include/asm/mach-sead3/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
new file mode 100644
index 000000000000..7c6931d5f45f
--- /dev/null
+++ b/arch/mips/include/asm/mach-sead3/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#define MIPS_CACHE_SYNC_WAR 1
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 1
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */