diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-04 01:27:48 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 02:10:37 +0300 |
| commit | 9b26616c8d9dae53fbac7f7cb2c6dd1308102976 (patch) | |
| tree | d4249bd953d4fa955cecd1283cc0f518df83f8a2 /arch/mips/include/asm/fpu.h | |
| parent | 232b6ec5df874236166fb0167cd473601a631715 (diff) | |
| download | linux-9b26616c8d9dae53fbac7f7cb2c6dd1308102976.tar.xz | |
MIPS: Respect the ISA level in FCSR handling
Define the central place the default FCSR value is set from, initialised
in `cpu_probe'. Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.
Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused. For ptrace(2) it's just sanity.
[ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.]
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/fpu.h')
| -rw-r--r-- | arch/mips/include/asm/fpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index dd083e999b08..83d50d563a0f 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -30,7 +30,7 @@ struct sigcontext; struct sigcontext32; -extern void _init_fpu(void); +extern void _init_fpu(unsigned int); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); @@ -182,6 +182,7 @@ static inline void lose_fpu(int save) static inline int init_fpu(void) { + unsigned int fcr31 = current->thread.fpu.fcr31; int ret = 0; if (cpu_has_fpu) { @@ -192,7 +193,7 @@ static inline int init_fpu(void) return ret; if (!cpu_has_fre) { - _init_fpu(); + _init_fpu(fcr31); return 0; } @@ -206,7 +207,7 @@ static inline int init_fpu(void) config5 = clear_c0_config5(MIPS_CONF5_FRE); enable_fpu_hazard(); - _init_fpu(); + _init_fpu(fcr31); /* Restore FRE */ write_c0_config5(config5); |