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| author | Ralf Baechle <ralf@linux-mips.org> | 2012-09-28 18:25:52 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-09-28 18:25:52 +0400 |
| commit | 77a0d763c461da81c2a3fc9a7e58162a40854a1a (patch) | |
| tree | bc5ca1d08c8f9b98fd8c8726e88788d4fc618118 /arch/mips/include/asm/cpu.h | |
| parent | 8922c9b4b2e3b1b845b46e8da61ad228d8f1b121 (diff) | |
| parent | 05857c64ecf897209c16ffad9bb3e8d359dd5dca (diff) | |
| download | linux-77a0d763c461da81c2a3fc9a7e58162a40854a1a.tar.xz | |
Merge branch 'rixi-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f21b7c04e95a..1037d54f0597 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -319,6 +319,7 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ +#define MIPS_CPU_RIXI 0x00400000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings |