diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2013-09-25 20:21:26 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-10-30 00:25:24 +0400 |
| commit | 14bd8c082016cd1f67fdfd702e4cf6367869a712 (patch) | |
| tree | b4d517e79c58fd3c665286b39ddb1801890f2cb0 /arch/mips/include/asm/cacheops.h | |
| parent | 7b784c634b4147345b46251884be6be4bd45fd43 (diff) | |
| download | linux-14bd8c082016cd1f67fdfd702e4cf6367869a712.tar.xz | |
MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.
It was ugly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 0644c985d153..c75025f27c20 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -20,11 +20,7 @@ #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else #define Hit_Invalidate_I 0x10 -#endif #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 @@ -84,4 +80,9 @@ #define Index_Store_Data_D 0x1d #define Index_Store_Data_S 0x1f +/* + * Loongson2-specific cacheops + */ +#define Hit_Invalidate_I_Loongson23 0x00 + #endif /* __ASM_CACHEOPS_H */ |