diff options
author | Paul Burton <paul.burton@imgtec.com> | 2015-09-22 21:56:38 +0300 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 10:35:47 +0300 |
commit | e81a8c7dabac05d444eda315ff1a747b0fe38396 (patch) | |
tree | c27dd399b540f377680163ce0fd6015d21404f7a /arch/mips/boot/dts/mti | |
parent | ea050714bc3656a25b4b5fc73f3682532c7180eb (diff) | |
download | linux-e81a8c7dabac05d444eda315ff1a747b0fe38396.tar.xz |
MIPS: Malta: Setup RAM regions via DT
Move memory configuration to be performed via device tree for the Malta
board. This moves more Malta specific code to malta-dtshim.c, leaving
the rest of the mti-malta code a little more board-agnostic. This will
be useful to share more code between boards, with the device tree
providing the board specifics as intended.
Since we can't rely upon Malta boards running a bootloader capable of
handling devictrees & filling in the required information, a piece of
shim code (malta_dt_shim) is added to consume the (e)memsize variables
provided as part of the bootloader environment (or on the kernel command
line) then generate the DT memory node using the provided values.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-kernel@vger.kernel.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Patchwork: https://patchwork.linux-mips.org/patch/11222/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/boot/dts/mti')
-rw-r--r-- | arch/mips/boot/dts/mti/malta.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mti/malta.dts b/arch/mips/boot/dts/mti/malta.dts index c678115f5b7f..b18c46637d21 100644 --- a/arch/mips/boot/dts/mti/malta.dts +++ b/arch/mips/boot/dts/mti/malta.dts @@ -1,5 +1,9 @@ /dts-v1/; +/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */ +/memreserve/ 0x00001000 0x000ef000; /* YAMON */ +/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ + / { #address-cells = <1>; #size-cells = <1>; |