diff options
| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2010-02-24 19:40:21 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 14:53:43 +0300 |
| commit | 11b897cf84c37e6522db914793677e933ef311fb (patch) | |
| tree | b9d69cea86b2c1673f30332ff9b3944dc00bfc9b /arch/mips/alchemy/common/setup.c | |
| parent | b9b37787d24cca9fbd63f767663e9439fa69aa22 (diff) | |
| download | linux-11b897cf84c37e6522db914793677e933ef311fb.tar.xz | |
MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus
area. Currently, addresses at the far end of the 32bit area are assumed
to belong to the PCMCIA area and fixed up to the real 36bit address before
being passed to ioremap().
A previous commit enabled 64 bit physical size for the resource datatype on
Alchemy and this allows to use the correct 36bit addresses when registering
the PCMCIA sockets.
This patch removes the 32-to-36bit address fixup and registers the Alchemy
demo board pcmcia socket with the correct 36bit physical addresses.
Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet
card.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/994/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common/setup.c')
| -rw-r--r-- | arch/mips/alchemy/common/setup.c | 32 |
1 files changed, 7 insertions, 25 deletions
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 193ba166affd..561e5da2658b 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -69,38 +69,20 @@ void __init plat_mem_setup(void) iomem_resource.end = IOMEM_RESOURCE_END; } -#if defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) /* This routine should be valid for all Au1x based boards */ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) { + u32 start = (u32)Au1500_PCI_MEM_START; + u32 end = (u32)Au1500_PCI_MEM_END; + /* Don't fixup 36-bit addresses */ if ((phys_addr >> 32) != 0) return phys_addr; -#ifdef CONFIG_PCI - { - u32 start = (u32)Au1500_PCI_MEM_START; - u32 end = (u32)Au1500_PCI_MEM_END; - - /* Check for PCI memory window */ - if (phys_addr >= start && (phys_addr + size - 1) <= end) - return (phys_t) - ((phys_addr - start) + Au1500_PCI_MEM_START); - } -#endif - - /* - * All Au1xx0 SOCs have a PCMCIA controller. - * We setup our 32-bit pseudo addresses to be equal to the - * 36-bit addr >> 4, to make it easier to check the address - * and fix it. - * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. - * The pseudo address we use is 0xF400 0000. Any address over - * 0xF400 0000 is a PCMCIA pseudo address. - */ - if ((phys_addr >= PCMCIA_ATTR_PSEUDO_PHYS) && - (phys_addr < PCMCIA_PSEUDO_END)) - return (phys_t)(phys_addr << 4); + /* Check for PCI memory window */ + if (phys_addr >= start && (phys_addr + size - 1) <= end) + return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); /* default nop */ return phys_addr; |