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| author | Michal Simek <monstr@monstr.eu> | 2010-02-08 18:41:38 +0300 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2012-03-23 12:28:19 +0400 |
| commit | e02db0aa3e1976ae4e23a66077d252a2f3ba74c7 (patch) | |
| tree | ed16439c89abca6be4770f654c7c458ff0f6512f /arch/microblaze/kernel/misc.S | |
| parent | 1451d1d88b9aa32ac9ee54180239e9b34b6f9e86 (diff) | |
| download | linux-e02db0aa3e1976ae4e23a66077d252a2f3ba74c7.tar.xz | |
microblaze: Handle TLB skip size dynamically
This patch fix the problem with rootfs on JFFS2 with early printk
console turned on.
The origin version used TLB63 for temporary early printk mapping.
The code expect that kernel is not able to use all 64 TLB entries
till early printk console is remapped by ioremap. After that
temporary mapping on TLB63 is silently lost.
This expectation give the opportunity to have early console pretty
early.
Microblaze systems with JFFS2 rootfs with early printk console turned on
used more than 64 TLB entries before kernel can remap early console.
Based on that kernel does access to bad area because early printk mapping
is rewritten.
This patch introduces tlb_skip variable which dynamically stores number
of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1
should be skipped.
MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start.
They can be used for user purpose.
TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID).
Also clean TLBLO when kernel starts.
For specific kernel sizes kernel can use just one TLB. Detect this case
and use the second TLB for general purpose.
Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE.
Export tlb_skip size through debugfs.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/kernel/misc.S')
| -rw-r--r-- | arch/microblaze/kernel/misc.S | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S index c9090d7973f6..1dafddeb8a0b 100644 --- a/arch/microblaze/kernel/misc.S +++ b/arch/microblaze/kernel/misc.S @@ -29,16 +29,16 @@ .type _tlbia, @function .align 4; _tlbia: - addik r12, r0, MICROBLAZE_TLB_SIZE - 1 /* flush all entries (63 - 3) */ + lwi r12, r0, tlb_skip; /* isync */ _tlbia_1: mts rtlbx, r12 nop mts rtlbhi, r0 /* flush: ensure V is clear */ nop - addik r11, r12, -MICROBLAZE_TLB_SKIP + rsubi r11, r12, MICROBLAZE_TLB_SIZE - 1 bneid r11, _tlbia_1 /* loop for all entries */ - addik r12, r12, -1 + addik r12, r12, 1 /* sync */ rtsd r15, 8 nop @@ -75,7 +75,7 @@ early_console_reg_tlb_alloc: * Load a TLB entry for the UART, so that microblaze_progress() can use * the UARTs nice and early. We use a 4k real==virtual mapping. */ - ori r4, r0, 63 + lwi r4, r0, tlb_skip mts rtlbx, r4 /* TLB slot 63 */ or r4,r5,r0 @@ -89,6 +89,11 @@ early_console_reg_tlb_alloc: nop mts rtlbhi,r5 /* Load the tag portion of the entry */ nop + + lwi r5, r0, tlb_skip + addik r5, r5, 1 + swi r5, r0, tlb_skip + rtsd r15, 8 nop |