diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2009-05-06 08:28:25 +0400 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-16 03:43:48 +0400 |
| commit | e47cc3d6acacffdc673779a44c21a4a12b20db23 (patch) | |
| tree | c9ee91eaa1dcd12092e56b84deac38eae921e551 /arch/m68k | |
| parent | 91b1b94f88219ea1b747264f4f6995a1202566cb (diff) | |
| download | linux-e47cc3d6acacffdc673779a44c21a4a12b20db23.tar.xz | |
m68knommu: mask off all interrupts in ColdFire intc-simr controller
The ColdFire intc-simr interrupt controller should mask off all
interrupt sources at init time. Doing it here instead of separately
in each platform setup.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/m532xsim.h | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 41c57e0f445a..021a0e155270 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -56,8 +56,6 @@ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ -#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ - #define MCFINTC0_SIMR 0xFC04801C #define MCFINTC0_CIMR 0xFC04801D #define MCFINTC0_ICR0 0xFC048040 @@ -70,37 +68,6 @@ /* - * Macro to set IMR register. It is 32 bits on the 5307. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - -#define mcf_getiprl() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL)) - -#define mcf_getiprh() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH)) - - -#define mcf_enable_irq0(irq) \ - *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq); - -#define mcf_enable_irq1(irq) \ - *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq); - -#define mcf_disable_irq0(irq) \ - *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq); - -#define mcf_disable_irq1(irq) \ - *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq); - -/* * Define the Cache register flags. */ #define CACR_EC (1<<31) |