diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2012-07-15 15:55:01 +0400 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 17:33:47 +0400 |
| commit | e1e362dc074c2981e7f78d26bf38a4f14be52ecd (patch) | |
| tree | 04a5e228b586561c274d1267b907f5b062ee0018 /arch/m68k/include | |
| parent | 6a3a786d02172b34d0ffba6f80bd1150da51125d (diff) | |
| download | linux-e1e362dc074c2981e7f78d26bf38a4f14be52ecd.tar.xz | |
m68knommu: make ColdFire SYPCR and RSR register definitions absolute addresses
Make all definitions of the ColdFire Reset and System registers absolute
addresses. Currently some are relative to the MBAR peripheral region.
The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the abolsute
address - factoring out whether it is an offset into a peripheral region.
This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/m5206sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m525xsim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m5407sim.h | 4 |
5 files changed, 10 insertions, 10 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index e8bae33aed60..d67ce08e508d 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -43,8 +43,8 @@ #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ -#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index d0aa7f27a311..e57785de8a2a 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -25,8 +25,8 @@ /* * Define the 5249 SIM register set addresses. */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h index 0d6d192355ca..05876cc95dde 100644 --- a/arch/m68k/include/asm/m525xsim.h +++ b/arch/m68k/include/asm/m525xsim.h @@ -26,8 +26,8 @@ /* * Define the 525x SIM register set addresses. */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 255f7f3120d9..5709de5b8289 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -23,8 +23,8 @@ /* * Define the 5307 SIM register set addresses. */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index afdd56325ae7..622ebface9b3 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -23,8 +23,8 @@ /* * Define the 5407 SIM register set addresses. */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ +#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ |