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| author | Hirokazu Takata <takata@linux-m32r.org> | 2006-01-06 11:18:41 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-06 19:33:43 +0300 |
| commit | 9287d95ea194abf32fab24c6909f8ea55ab0292f (patch) | |
| tree | 4c00a6866d1da4fac5b5ca3bdb86eb2170a3fbf4 /arch/m32r/kernel/entry.S | |
| parent | 60c83c77c4a6a399d55e4f9ad156bccdfe51c96b (diff) | |
| download | linux-9287d95ea194abf32fab24c6909f8ea55ab0292f.tar.xz | |
[PATCH] m32r: Support M32104UT target platform
This patch is for supporting a new target platform, Renesas M32104UT
evaluation board.
The M32104UT is an eval board based on an uT-Engine specification. This board
has an MMU-less M32R family processor, M32104.
http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf
This board is one of the most popular M32R platform, so we have ported
Linux/M32R to it.
Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/m32r/kernel/entry.S')
| -rw-r--r-- | arch/m32r/kernel/entry.S | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S index f6d4a5821a2c..3871b65f0c82 100644 --- a/arch/m32r/kernel/entry.S +++ b/arch/m32r/kernel/entry.S @@ -315,7 +315,7 @@ ENTRY(ei_handler) mv r1, sp ; arg1(regs) #if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ - || defined(CONFIG_CHIP_OPSP) + || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) ; GET_ICU_STATUS; seth r0, #shigh(M32R_ICU_ISTS_ADDR) @@ -541,7 +541,20 @@ check_int2: bra check_end .fillinsn check_end: -#endif /* CONFIG_PLAT_OPSPUT */ +#elif defined(CONFIG_PLAT_M32104UT) + add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt + bnez r2, check_end + ; read ICU status register of PLD + seth r0, #high(PLD_ICUISTS) + or3 r0, r0, #low(PLD_ICUISTS) + lduh r0, @r0 + slli r0, #21 + srli r0, #27 ; ISN + addi r0, #(M32104UT_PLD_IRQ_BASE) + bra check_end + .fillinsn +check_end: +#endif /* CONFIG_PLAT_M32104UT */ bl do_IRQ #endif /* CONFIG_SMP */ ld r14, @sp+ |