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author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 13:04:11 +0300 |
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committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 15:09:28 +0300 |
commit | 5b0b14e550a006b4d093619e7517923872bcc218 (patch) | |
tree | 377ee63c9a0f543145721409286e38bc59ec4511 /arch/loongarch/include/asm/bitrev.h | |
parent | f2ac457a61389b7769aad8295027cbe0f91c5b80 (diff) | |
download | linux-5b0b14e550a006b4d093619e7517923872bcc218.tar.xz |
LoongArch: Add atomic/locking headers
Add common headers (atomic, bitops, barrier and locking) for basic
LoongArch support.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/bitrev.h')
-rw-r--r-- | arch/loongarch/include/asm/bitrev.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/bitrev.h b/arch/loongarch/include/asm/bitrev.h new file mode 100644 index 000000000000..46f275b9cdf7 --- /dev/null +++ b/arch/loongarch/include/asm/bitrev.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#ifndef __LOONGARCH_ASM_BITREV_H__ +#define __LOONGARCH_ASM_BITREV_H__ + +#include <linux/swab.h> + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + u32 ret; + + asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(__swab32(x))); + return ret; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + u16 ret; + + asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(__swab16(x))); + return ret; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + u8 ret; + + asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(x)); + return ret; +} + +#endif /* __LOONGARCH_ASM_BITREV_H__ */ |