diff options
| author | Fenghua Yu <fenghua.yu@intel.com> | 2008-10-17 23:14:13 +0400 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2008-10-17 23:14:13 +0400 |
| commit | 62fdd7678a26efadd6ac5c2869543caff77d2df0 (patch) | |
| tree | 0dd67208590c4540ff6a4476579a55bcac0d1fce /arch/ia64/include/asm/cacheflush.h | |
| parent | 6bb7a935489dab20802dde6c2cb7d8582f4849bf (diff) | |
| download | linux-62fdd7678a26efadd6ac5c2869543caff77d2df0.tar.xz | |
[IA64] Add Variable Page Size and IA64 Support in Intel IOMMU
The patch contains Intel IOMMU IA64 specific code. It defines new
machvec dig_vtd, hooks for IOMMU, DMAR table detection, cache line flush
function, etc.
For a generic kernel with CONFIG_DMAR=y, if Intel IOMMU is detected,
dig_vtd is used for machinve vector. Otherwise, kernel falls back to
dig machine vector. Kernel parameter "machvec=dig" or "intel_iommu=off"
can be used to force kernel to boot dig machine vector.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/include/asm/cacheflush.h')
| -rw-r--r-- | arch/ia64/include/asm/cacheflush.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/ia64/include/asm/cacheflush.h b/arch/ia64/include/asm/cacheflush.h index afcfbda76e20..c8ce2719fee8 100644 --- a/arch/ia64/include/asm/cacheflush.h +++ b/arch/ia64/include/asm/cacheflush.h @@ -34,6 +34,8 @@ do { \ #define flush_dcache_mmap_unlock(mapping) do { } while (0) extern void flush_icache_range (unsigned long start, unsigned long end); +extern void clflush_cache_range(void *addr, int size); + #define flush_icache_user_range(vma, page, user_addr, len) \ do { \ |