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| author | Brett Creeley <brett.creeley@intel.com> | 2019-11-08 17:23:23 +0300 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2019-11-23 00:15:04 +0300 |
| commit | e25f9152bc07de534b2b590ce6c052ea25dd8900 (patch) | |
| tree | fa0ca381a50a43abcb762b35cbf83324f9b11475 /arch/c6x/boot | |
| parent | 1f9639d2fb9188a59acafae9dea626391c442a8d (diff) | |
| download | linux-e25f9152bc07de534b2b590ce6c052ea25dd8900.tar.xz | |
ice: Fix setting coalesce to handle DCB configuration
Currently there can be a case where a DCB map is applied and there are
more interrupt vectors (vsi->num_q_vectors) than Rx queues (vsi->num_rxq)
and Tx queues (vsi->num_txq). If we try to set coalesce settings in this
case it will report a false failure. Fix this by checking if vector index
is valid with respect to the number of Tx and Rx queues configured.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'arch/c6x/boot')
0 files changed, 0 insertions, 0 deletions