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| author | Sonic Zhang <sonic.zhang@analog.com> | 2010-08-05 11:49:26 +0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-18 11:01:04 +0300 |
| commit | c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa (patch) | |
| tree | 8f3980f69cba2e3269aa9688426fca95be56d7a6 /arch/blackfin/mach-common/smp.c | |
| parent | 6f546bc3ac9eedbf770bf3bcbc45ce2ea32c94ad (diff) | |
| download | linux-c6345ab1a3d17f4b6c80ac79d7fb0f006b32fdaa.tar.xz | |
Blackfin: SMP: work around anomaly 05000491
In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram. The trouble with multi-core systems is that all
L1 sram is visible only to the active core. So we can't just place the
functions into L1 and call it directly. We need to setup a jump table and
place the entry point in external memory. This will call the right func
based on the active core.
In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/smp.c')
| -rw-r--r-- | arch/blackfin/mach-common/smp.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 5f7617d66905..6e17a265c4d3 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -40,6 +40,10 @@ */ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); +#ifdef CONFIG_ICACHE_FLUSH_L1 +unsigned long blackfin_iflush_l1_entry[NR_CPUS]; +#endif + void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, *init_saved_dcplb_fault_addr_coreb; |