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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-10-25 17:12:27 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-04 17:58:51 +0300 |
| commit | 6060e8df517847bf445ebc61de7d4d9c7faae990 (patch) | |
| tree | 64a86fe9a921584e38b7ce24521248b8461171c6 /arch/arm | |
| parent | ea201dbb78651c71c56e440b8b3132906bc7456d (diff) | |
| download | linux-6060e8df517847bf445ebc61de7d4d9c7faae990.tar.xz | |
ARM: I-cache: flush executable mappings in flush_cache_range()
Dirk Behme reported instability on ARM11 SMP (VIPT non-aliasing cache)
caused by the dynamic linker changing protection on text pages to write
GOT entries. The problem is due to an interaction between the write
faulting code providing new anonymous pages which are incoherent with
the I-cache due to write buffering, and the I-cache not having been
invalidated.
a4db94d plugs the hole with the data cache coherency. This patch
provides the other half of the fix by flushing the I-cache in
flush_cache_range() for VM_EXEC VMAs (which is what we have when the
region is being made executable again.) This ensures that the I-cache
will be up to date with the newly COW'd pages.
Note: if users are writing instructions, then they still need to use
the ARM sys_cacheflush API to ensure that the caches are correctly
synchronized.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mm/flush.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index f8feb5d919fe..329594e760cd 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -66,10 +66,9 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned : : "r" (0) : "cc"); - __flush_icache_all(); } - if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) + if (vma->vm_flags & VM_EXEC) __flush_icache_all(); } |